Printed wiring board and manufacturing method thereof
AssigneeIbiden Co., Ltd.
InventorsToru Nakai, Masanori Tamaki
Life of this patent
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Abstract
A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a second conductive circuit positioned adjacent to each other, and the first and second conductive circuits satisfy a formula, 0.10 T≦|W1−W2|≦0.73 T, where W1 represents an upper conductive circuit space between the first and second conductive circuits, W2 represents a lower conductive circuit space between the first and second conductive circuits, and T represents a thickness of the first and second conductive circuits.
Claims21
A printed wiring board comprising:
- a core substrate including an insulation layer and a conductive layer formed on the insulation layer;
- and
- a build-up wiring layer formed on the core substrate, the build-up wiring layer including:
- a first interlayer resin insulation layer,
- a first plurality of conductive circuits formed on the first interlayer resin insulation layer,
- a second interlayer resin insulation layer formed on the first interlayer resin insulation layer and on the first plurality of conductive circuits such that spaces between the first plurality of conductive circuits are filled with a material of the second interlayer resin insulation layer,
- wherein the first plurality of conductor circuits including a first conductive circuit and a second conductive circuit positioned adjacent to the first conductive circuit,
- the first and the second conductive circuits each have a cross section that is substantially trapezoidal and
- the first and the second conductive circuits are configured to satisfy a formula (1),
- 0.10T≦|W1−W2|≦0.73T (1)
- wherein W1 represents a width of a space between upper surfaces of the first and second conductive circuits, W2 represents a width of a space between lower surfaces of the first and second conductive circuits, and T represents a thickness of each of the first and second conductive circuit.
Dependencies are inferred from the claim text.