Twisted dual-substrate orientation (DSO) substrates

A method for forming a semiconductor structure having dual substrates on a wafer, comprising:

• forming a first semiconductor layer having a first crystal orientation;
• forming a second semiconductor layer over at least part of the first semiconductor layer, wherein the second semiconductor layer is electrically isolated from the first semiconductor layer by a buried insulator layer and where the second semiconductor layer has a crystal orientation that is rotated 45 degrees with respect to the first crystal orientation of the first semiconductor layer;
• forming a first trench opening that exposes the first semiconductor layer by removing the buried insulator layer and the second semiconductor layer in a first region;
• forming a first insulator layer to fill in the first trench opening;
• then
• forming a second trench opening in the first insulator layer by removing at least the first insulator layer in a second region within the first region to expose the first semiconductor layer;
• then
• filling at least part of a second trench opening that exposes the first semiconductor layer by epitaxially growing a first epitaxial semiconductor layer on at least an exposed surface of the first semiconductor layer;
• and
• selectively etching the first epitaxial semiconductor layer and the second semiconductor layer to form FinFET channel regions from the first epitaxial semiconductor layer and the second semiconductor layer.

A method for fabricating FET devices on a twisted dual substrate, comprising:

• providing a second semiconductor layer that is isolated from an underlying first semiconductor layer by at least a buried insulator layer, where the second semiconductor layer is crystallographically rotated with respect to the underlying first semiconductor layer;
• forming a shallow trench isolation region in a first trench opening that exposes the first semiconductor layer in a first area by filling the first trench opening with an insulating material;
• then
• exposing the first semiconductor layer by forming a second trench opening in the shallow trench isolation region in a second area contained within the first area;
• then
• epitaxially growing a first epitaxial semiconductor layer from the second area, where the first epitaxial semiconductor layer is isolated from the second semiconductor layer by the shallow trench isolation region;
• selectively etching the first epitaxial semiconductor layer to form first CMOS FinFET channel regions and planar channel regions from the first epitaxial semiconductor layer;
• and
• selectively etching the second semiconductor layer to form second CMOS FinFET channel regions and planar channel regions from the second semiconductor layer.