Parallel data processing apparatus
AssigneeClearspeed Technology Limited
InventorsDave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer
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Abstract
A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.
Claims3
A register score-boarding unit for use in an array controller for controlling the operation of a SIMD (single instruction multiple data) array of processing elements in which the processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items, the array controller comprising a processing element instruction sequencer for handling data processing instructions and a data transfer controller for handling data transfer instructions, the register score-boarding unit comprising:
- means for maintaining the appearance of serial instruction execution while achieving parallel operation between the processing element instruction sequencer and the data transfer controller;
- an enable stack to determine whether a processing element is permitted to process data supplied to it;
- and
- means to stall a load/store instruction, in response to an executing microcode-instruction that modifies the enable stack.
Dependencies are inferred from the claim text.