Tri-gate field-effect transistors formed by aspect ratio trapping
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorAnthony J. Lochtefeld
Life of this patent
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Abstract
Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
Claims23
A method for forming a structure, the method comprising the steps of:
- forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
- defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
- forming, in the trench, a crystalline material including a first layer comprising a second semiconductor material and a second layer comprising a third semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
- removing a portion of the dielectric layer to expose a side portion of the crystalline material;
- and
- defining a gate over the crystalline material.
A method for forming a structure, the method comprising the steps of:
- forming a dielectric layer over a semiconductor substrate comprising a first semiconductor material;
- defining a trench in the dielectric layer, the trench (i) extending to a surface of the substrate, and (ii) having a height h and a width w, the ratio of h to w being ≧0.5;
- forming, in the trench, at least one crystalline material layer comprising a second semiconductor material having a lattice mismatch with the first semiconductor material, a majority of dislocation defects in the second semiconductor material terminating within the trench;
- removing a portion of the dielectric layer to expose a side portion of the crystalline material;
- and
- defining a gate over the crystalline material.
A method for forming a structure, the method comprising:
- removing a portion of a semiconductor substrate comprising a first semiconductor material to define a fin;
- depositing a dielectric layer over the substrate and the fin;
- planarizing the dielectric layer such that a top surface thereof is substantially co-planar with a top surface of the fin;
- defining a trench by removing at least a portion of the fin, the trench having a height h and a width w, the ratio of h to w being ≧0.5;
- forming, in the trench, a crystalline material comprising a second semiconductor material lattice-mismatched to the first semiconductor material, a majority of dislocation defects in the crystalline material terminating within the trench;
- removing a portion of the dielectric layer to expose a side portion of the crystalline material;
- and
- defining a gate over the second semiconductor material.
Dependencies are inferred from the claim text.