Processor having parallel vector multiply and reduce operations with sequential semantics

An integrated circuit comprising at least one multi-threaded vector processor, the multi-threaded vector processor comprising:

• a plurality of vector arithmetic units for performing parallel concurrent vector operations on vectors comprising vector elements;
• a vector accumulator unit;
• and
• a vector reduction unit coupled between the plurality of vector arithmetic units and the vector accumulator unit, the vector reduction unit being pipelined and configured to receive products of vector elements from the vector arithmetic units and a first accumulator value from the vector accumulator unit;
• wherein the vector reduction unit is operative to process the products and the first accumulator value, and to generate a second accumulator value for delivery to the vector accumulator unit;
• wherein the multi-threaded vector processor implements a plurality of vector multiply and reduce instructions having guaranteed sequential semantics such that computation results of a vector multiply and reduce instruction is the same as that which is produced using a corresponding sequence of individual instructions;
• and
• wherein a vector multiply and reduce instruction computed for a given thread is executed concurrently with operations from other threads, the number of cycles between execution of the vector multiply and reduce instruction from the given thread being greater than or equal to a number of pipeline stages in the vector reduction unit plus any additional cycles needed to write to and read from the vector accumulator unit.

An apparatus for use in a multi-threaded vector processor comprising a plurality of vector arithmetic units for performing parallel concurrent vector operations on vectors comprising vector elements and a vector accumulator unit, the apparatus comprising:

• a vector reduction unit coupled between the plurality of vector arithmetic units and the vector accumulator unit, the vector reduction unit being configured to receive products of vector elements from the arithmetic units and a first accumulator value from the vector accumulator unit;
• wherein the vector reduction unit is pipelined and operative to process the products and the first accumulator value, and to generate a second accumulator value for delivery to the vector accumulator unit;
• wherein the multi-threaded vector processor implements a plurality of vector multiply and reduce instructions having guaranteed sequential semantics such that computation results of a vector multiply and reduce instruction is the same as that which is produced using a corresponding sequence of individual instructions;
• and
• wherein a vector multiply and reduce instruction computed for a given thread is executed concurrently with operations from other threads, the number of cycles between execution of the vector multiply and reduce instruction from the given thread being greater than or equal to a number of pipeline stages in the vector reduction unit plus any additional cycles needed to write to and read from the vector accumulator unit.