Circuits and methods for a multi-differential embedded-clock channel
OwnerJames Ridenour McGeeinventor
Life of this patent
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Abstract
An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.
Claims29
An interface circuit for a multi-differential embedded-clock channel for communicating data, comprising:
- a first plurality of first signals, wherein the first plurality is at least four;
- a second plurality of second signals, wherein the second plurality is at least four;
- and
- a multi-differential amplifier coupled to the first and second signals, the multi-differential amplifier adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals, wherein each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.
A method for communicating data using a multi-differential embedded-clock channel, comprising:
- amplifying a plurality of differential transitions using a first multi-differential amplifier;
- serially transmitting the differential transitions from the first multi-differential amplifier to the channel, wherein the differential transitions are between all combinations of two of at least four signals of the channel;
- serially receiving the differential transitions from the channel to a second multi-differential amplifier;
- and
- amplifying the differential transitions received from the channel using the second multi-differential amplifier.
A system for communicating data using a multi-differential embedded-clock channel, comprising:
- means for amplifying a plurality of differential transitions using a first multi-differential amplifier;
- means for serially transmitting the differential transitions from the first multi-differential amplifier to the channel, wherein the differential transitions are between all combinations of two of at least four signals of the channel;
- means for serially receiving the differential transitions from the channel to a second multi-differential amplifier;
- and
- means for amplifying the differential transitions received from the channel using the second multi-differential amplifier.
A circuit, comprising a transceiver for a multi-differential embedded-clock channel for communicating first and second data, the transceiver including:
- a first multi-differential amplifier coupled to at least four first signals of the channel and adapted to amplify, for all combinations of two of the first signals, a plurality of first differential transitions between the two of the first signals, wherein each of a plurality of first symbols of the first data has a corresponding one of the first differential transitions, and the amplification of the first differential transitions is serially transmitted to the channel via the first signals;
- and
- a second multi-differential amplifier coupled to at least four second signals of the channel and adapted to amplify, for all combinations of two of the second signals, a plurality of second differential transitions between the two of the second signals, wherein each of a plurality of second symbols of the second data has a corresponding one of the second differential transitions, and the second differential transitions are serially received from the channel via the second signals.
An amplification circuit, comprising:
- four input signal lines for serially receiving a first plurality of differential transitions, wherein for all combinations of two of the four input signal lines, the first differential transitions include at least one differential transition between the two input signal lines, and each of the first differential transitions is a differential transition between two of the four input signal lines;
- an amplifier coupled to receive the first differential transitions from the four input signal lines, the amplifier generating a second plurality of differential transitions from the first differential transitions, the amplifier generating a respective one of the second differential transitions for each of the first differential transitions, wherein the respective second differential transition is an amplification of the first differential transition;
- and
- four output signal lines coupled to the amplifier for serially transmitting the second differential transitions, wherein for all combinations of two of the four output signal lines, the second differential transitions include at least one differential transition between the two output signal lines, and each of the second differential transitions is a differential transition between two of the four output signal lines.
Dependencies are inferred from the claim text.