Digital phase locked loop with dithering

A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator;
• and
• a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference clock;
• wherein the dithering circuit is operable to generate a plurality of short sequence dither signals having different periods and noise shape characteristics, and further comprising a control register coupled to the dithering circuit operable to select one of the plurality of short sequence dither signals for injecting into the reference clock.

A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator;
• a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference clock;
• and
• an additional dithering circuit coupled to the reference clock operable to inject a continuous dither signal.

A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator;
• a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference clock;
• and
• a loop filter circuit being coupled between the phase detection circuit and the controllable oscillator, the loop filter operable to provide filtered frequency tuning adjustment to the controllable oscillator, wherein the loop filter is operable to filter out the short sequence dither signal.

A cellular telephone comprising a phase locked loop (PLL), wherein the PLL forms a local oscillator and comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator;
• a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference clock;
• and
• a data modulating input for providing data deviation commands operable to adjust the frequency of the controllable oscillator thereby providing frequency modulation of the local oscillator.

A cellular telephone comprising:

• a reference frequency generator for forming a reference clock;
• a transmitter connected to receive the reference clock, comprising:
• a phase locked loop (PLL), wherein the PLL comprises:
• a controllable oscillator for generating a radio frequency (RF) clock;
• phase detection circuit operational to provide phase error samples indicative of phase differences between the RF clock and the reference clock for controlling the controllable oscillator;
• a dithering circuit coupled to the reference clock operable to inject a short sequence dither into the reference clock;
• and
• a data modulating input for providing data deviation commands operable to adjust the frequency of the controllable oscillator thereby providing frequency modulation of the local oscillator.