Data processing apparatus including reconfigurable logic circuit

A generation system for generating hardware control information for controlling a reconfigurable logic circuit, the generation system comprising:

• a functional unit for generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application;
• and
• a functional unit for generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, wherein the functional unit for generating the circuit information includes generating information of the plurality of cycle-based circuits based on a control data flow graph for executing the application.

A computer implemented method of generating hardware control information for controlling a reconfigurable logic circuit, the method comprising the steps of:

• the computer generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application;
• and
• the computer generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, wherein the step of generating the hardware control information includes generating a piece of configuration selection information in each cycle and merging the piece of configuration selection information with a piece of cycle-based mapping information.