Digital phase locked loop with gear shifting

A system comprising a phase locked loop (PLL) having a loop gain and a phase margin, wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase difference between the RF clock and the reference clock for controlling the controllable oscillator;
• a programmable filter connected to receive the phase error samples and connected to provide a filtered output to the controllable oscillator, the programmable filter comprising a proportional loop gain control having a programmable loop coefficient (alpha) and an integral loop gain control having a programmable loop coefficient (rho);
• and
• wherein alpha and rho are configured to be programmatically changed simultaneously and wherein values of alpha and rho are selected to maintain an approximately constant ratio of alpha and square root of rho.

A system comprising a phase locked loop (PLL) having a loop gain and a phase margin, wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase difference between the RF clock and the reference clock for controlling the controllable oscillator;
• a programmable filter connected to receive the phase error samples and connected to provide a filtered output to the controllable oscillator, the programmable filter comprising a proportional loop gain control having a programmable loop coefficient (alpha) and an integral loop gain control having a programmable loop coefficient (rho);
• and
• wherein alpha and rho are configured to be programmatically changed simultaneously and wherein values for the alpha and rho are selected such that the loop gain is changed and the phase margin remains substantially unchanged.

A system comprising a phase locked loop (PLL) having a loop gain and a phase margin, wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase difference between the RF clock and the reference clock for controlling the controllable oscillator;
• a programmable filter connected to receive the phase error samples and connected to provide a filtered output to the controllable oscillator, the programmable filter comprising one or more linear filters each having a programmable linear filter coefficient, coupled to first receive the phase error samples, a proportional loop gain control having a programmable loop coefficient (alpha) and an integral loop gain control having a programmable loop coefficient (rho), wherein alpha and rho are configured to be programmatically changed simultaneously;
• and
• wherein the programmable filter coefficients are configured such that at least one linear filter coefficient is changed simultaneously with alpha and rho, such that bandwidth of the filter is changed and phase margin remains substantially unchanged.

A system comprising a phase locked loop (PLL) having a loop gain and a phase margin, wherein the PLL comprises:

• a frequency reference input for receiving a reference clock;
• a controllable oscillator for generating a radio frequency (RF) clock;
• a phase detection circuit operational to provide phase error samples indicative of phase difference between the RF clock and the reference clock for controlling the controllable oscillator;
• a programmable filter connected to receive the phase error samples and connected to provide a filtered output to the controllable oscillator, the programmable filter comprising one or more linear filters each having a programmable linear filter coefficient, coupled to first receive the phase error samples, a proportional loop gain control having a programmable loop coefficient (alpha) and an integral loop gain control having a programmable loop coefficient (rho), wherein alpha and rho are configured to be programmatically changed simultaneously;
• and
• wherein the programmable filter coefficients are configured such that at least one linear filter coefficient is changed before or after changing alpha and rho, such that bandwidth of the filter is changed and phase margin remains substantially unchanged.

A method for operating a phase locked loop having a loop gain and a phase margin, comprising:

• generating a radio frequency (RF) clock using a controllable oscillator;
• calculating phase error samples indicative of phase difference between the RF clock and a reference clock for controlling the controllable oscillator;
• filtering the phase error samples using a linear filter, a proportional loop gain controller and an integral loop gain controller;
• and
• changing bandwidth of the filter by changing a proportional loop gain coefficient (alpha) and an integral loop gain coefficient (rho) simultaneously such that the loop gain is changed and the phase margin remains above a certain limit, wherein values of alpha and rho are selected to maintain an approximately constant ratio of alpha over square root of the rho.

A method for operating a phase locked loop having a loop gain and a phase margin, comprising:

• generating a radio frequency (RF) clock using a controllable oscillator;
• calculating phase error samples indicative of phase difference between the RF clock and a reference clock for controlling the controllable oscillator;
• filtering the phase error samples using one or more linear filters each having a programmable linear filter coefficient, a proportional loop gain controller and an integral loop gain controller;
• and
• changing bandwidth of the filter by changing one or more of the linear filter coefficients, a proportional loop gain coefficient (alpha) and an integral loop gain coefficient (rho) simultaneously such that the loop gain is changed and the phase margin remains above a certain limit, wherein values for alpha, rho and the coefficients for the linear filters are selected to maintain an approximately constant relationship of a PLL damping factor.

A cellular telephone comprising:

• a reference frequency generator for forming a reference clock;
• a transmitter connected to receive the reference clock, comprising:
• a phase locked loop (PLL) having a loop gain and a phase margin, wherein the PLL comprises:
• a controllable oscillator for generating a radio frequency (RF) clock;
• phase detection circuit operational to provide phase error samples indicative of phase difference between the RF clock and the reference clock for controlling the controllable oscillator;
• a data modulating input for providing frequency deviation commands operable to adjust the frequency of the controllable oscillator thereby providing frequency modulation of the local oscillator;
• and
• a loop filter with a gear shifting circuit connected between the phase detection circuit and the controllable oscillator, wherein the gear shift circuit comprises:
• a proportional loop gain circuit having a coefficient alpha, the proportional gain circuit having an input for receiving a data stream and having an output;
• an integral gain circuit having a coefficient rho, the integral circuit having an input to receive the data stream and having an output coupled via an adder to the output of the proportional gain circuit;
• and
• a controllable circuit connected to provide alpha and rho, wherein alpha and rho are adjusted in unison to produce a gear shift operation.