High bandwidth cache-to-processing unit communication in a multiple processor/cache system

A processor/cache assembly, comprising:

• a processor die having first, second, third, and fourth processor units arranged in an array of processor units;
• first, second, third, and fourth sets of processor contact pads on a first major surface of the processor die, wherein the first, second, third, and fourth sets of processor contact pads are for carrying addresses from the first, second, third, and fourth processor units, respectively;
• a cache die having first, second, third, and fourth cache units arranged in an array of cache units;
• first, second, third, and fourth sets of cache contact pads on a first major surface of the cache die, wherein the first, second, third, and fourth sets of cache contact pads are for receiving addresses from the first, second, third, and fourth processor units, respectively, for the use of the first, second, third, and fourth cache units, respectively.

A processor/cache assembly, comprising:

• a first semiconductor die having an array of processing units, wherein:
• each processing unit of the array of processing units has a set of processor contact pads;
• the set of processor contact pads are conductive pads on a surface of the first semiconductor die;
• each set of processor contact pads is unique from the set of processor contact pads of all other processing units of the array of processing units;
• and
• each set of the processor contact pads includes a first subset of processor contact pads for address signals and a second subset of processor contact pads for data signals;
• a second semiconductor die having an array of cache units, wherein:
• each cache unit of the array of cache units has a set of cache contact pads;
• the set of cache contact pads are conductive pads on a surface external of the second semiconductor die;
• each set of cache contact pads is unique from the set of cache contact pads of all other cache units of the array of cache units;
• each set of the external contact pads includes a first subset of cache contact pads for address signals and a second subset of cache contact pads for data signals;
• the first subset of cache contact pads of each cache unit is connected to the first subset of processor contact pads of a unique one of the processor units;
• and
• the second subset of cache contact pads of each cache unit is connected to the second subset of processor contact pads of the processor unit to which its first subset of cache contact pads is connected;
• and
• an interposer between adjoining surfaces of the first die and the second die for connecting processor contact pads of at least one processing unit of the array of processing units to correlated cache contact pads of a correlated cache unit of the array of cache units.