Semiconductor device including a high-breakdown voltage MOS transistor
AssigneeRenesas Technology Corp.
InventorMasatoshi Taya
Life of this patent
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Abstract
On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.
Claims2
A semiconductor device, comprising:
- a first impurity region of a first conductivity type formed on a main surface of a semiconductor substrate;
- a first isolating insulation film formed on a surface of said first impurity region, the first isolating insulation film includes a portion formed to a predetermined depth from the main surface of the semiconductor substrate;
- a second impurity region of a second conductivity type formed at that portion of said first impurity region which is positioned immediately below said first isolating insulation film;
- a third impurity region of the second conductivity type formed at a surface of a portion of said first impurity region, spaced apart from said first isolating insulation film;
- a fourth impurity region of the second conductivity type formed on a portion of said first impurity region on a side opposite to said third impurity region with said first isolating insulation film positioned therebetween, said fourth impurity region of the second conductivity type spaced apart from said first isolating insulation film;
- a first gate electrode portion formed on that portion of said first impurity region which is sandwiched between said second impurity region and said third impurity region;
- and
- a second gate electrode portion formed on that portion of said first impurity region which is sandwiched between said second impurity region and said fourth impurity region,
- wherein the first gate electrode portion and the second gate electrode portion are configured for receiving voltages individually applied thereto, and the first gate electrode portion and second gate electrode portion are not electrically connected, and
- said first isolating insulation film is formed continuously between said first gate electrode portion and said second gate electrode portion.
Dependencies are inferred from the claim text.