Analog read and write paths in a solid state memory device
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Vishal Sarin
Life of this patent
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Abstract
A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
Claims22
An analog input/output data interface for interfacing between a controller circuit and a memory device having a memory array, the interface comprising:
- an analog interface that couples the memory device to the controller circuit;
- and
- an analog data cache, coupled between the analog interface and the memory array, for storing an analog signal representative of data wherein the analog interface and the analog data cache accept the analog signal from the controller circuit for storing in the memory array.
A memory device comprising:
- a memory array having a plurality of memory cells organized in columns coupled to bit lines;
- and
- an analog input/output data interface coupled to the memory array, the interface comprising a plurality of analog data paths, each analog data path comprising a storage element for storing an analog signal input to the memory device that is to be programmed into a selected memory cell of the memory array, the interface further comprising a comparator circuit coupled to the storage element and the selected memory cell, the comparator circuit configured to compare the stored analog signal with a voltage programmed into the selected memory cell and generate a programmed indication.
A NAND non-volatile memory device comprising:
- a memory array having a plurality of memory cells coupled to word lines and bit lines;
- an analog I/O interface coupled to the memory array through the word lines and bit lines, the interface comprising a plurality of analog data paths, each analog data path coupled to a different bit line and comprising:
- a first capacitive element for storing an analog input signal input to the memory device;
- a second capacitive element for storing a target voltage;
- and
- a comparator circuit for comparing the analog input signal with the target voltage and outputting an inhibit signal in response to the comparison;
- and
- a memory controller for generating control signals in response to the inhibit signal.
A method for operating a memory device having a plurality of analog data paths coupled to a memory array, the method comprising:
- storing an analog data signal in at least one analog data path of the plurality of data paths;
- biasing a word line of the memory array with a biasing voltage to program a selected memory cell with the analog data signal;
- biasing a bit line to enable programming of the selected memory cell;
- verifying a programmed voltage to which the selected memory cell is programmed;
- and
- inhibiting programming when the programmed voltage is equal to or greater than a target voltage indicative of the analog data signal.
Dependencies are inferred from the claim text.