Delay stabilization for skew tolerance
AssigneeFairchild Semiconductor Corporation
InventorDavid P. Morrill
Life of this patent
Estimating the term…
Abstract
In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.
Claims14
An integrated circuit comprising:
- at least first and second separate timing circuits that are created by the same fabrication process;
- wherein a first timing circuit is a clock and a second timing circuit is a delay circuit;
- a time specification for an at least first timing circuit is known,
- a first variable control circuit that controls the timing of at the least first clock timing circuit;
- a driver that outputs a control signal to the first variable control circuit;
- a trim value that is related to the fabrication process,
- wherein when the at least first timing circuit does not meet its time specification;
- the trim value is determined and applied to the driver so that the at least first timing circuit meets its timing specification;
- a second variable control circuit that controls the timing of a second timing circuit;
- and
- a second driver that outputs a second control signal to the second variable control circuit, wherein the trim value is applied to the second driver thereby trimming the timing of the second timing circuit to meet its timing specification, wherein the application of the trim value to the at least first and second timing circuits corrects for process, temperature and voltage variations.
A method for trimming an integrated circuit containing at least two separate timing circuits, wherein a first timing circuit is a clock and a second timing circuit is a delay circuit;
- wherein a time specification for at least a first timing circuit is known, the method comprising the steps of:
- creating the at least two timing circuits by the same fabrication process;
- wherein the fabrication process may be typical, fast, or slow;
- measuring the timing of at least first timing circuit;
- wherein the timing of the at least first timing circuit may be typical, too fast, or too slow;
- determining a trim value that is related to the fabrication process speeds;
- changing the timing of the at least one timing circuit to meet its time specification by applying the trim value to a first variable control circuit that controls the timing of the at least first timing circuit;
- and
- changing the timing of a second timing circuit to meet its time specification by applying the trim value to a second variable control circuit that controls the timing of the second timing circuit, wherein the application of the trim value to the at least first and second timing circuits corrects for process, temperature and voltage variations.
A method for fabricating an integrated circuit, the method comprising the steps of:
- creating at least first and second timing circuits, wherein a first timing circuit is a clock and a second timing circuit is a delay circuit, made by the same fabrication process;
- wherein the fabrication process may be fast, slow or typical process, wherein the at least first and second timing circuits each have a timing specification;
- measuring the timing of the first timing circuit;
- wherein the timing of the first timing circuit may be typical, too fast, or too slow with respect to its timing specification;
- determining a trim value that is related to the fabrication process speeds;
- applying the trim value to a first variable control circuit that controls the timing of the first timing circuit, wherein the first timing circuit meets its timing specification;
- and
- applying the trim value to a second variable control circuit that controls the timing of the second timing circuit, wherein the second timing circuit meets its timing specification, wherein the application of the trim value to the at least first and second timing circuits corrects for process, temperature and voltage variations.
Dependencies are inferred from the claim text.