Semiconductor device and semiconductor chips outputting a data strobe signal
AssigneeElpidia Memory, Inc.
InventorHideo Inaba
Life of this patent
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AssigneeElpidia Memory, Inc.
InventorHideo Inaba
Estimating the term…
High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.
A semiconductor device comprising:
A semiconductor chip that outputs a data signal and a data strobe signal indicative of an output timing of the data signal,
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor chip that outputs a data signal and a data strobe signal indicative of an output timing of the data signal, said semiconductor chip comprising:
Dependencies are inferred from the claim text.