# US 7,746,444 B2 · Array substrate, liquid crystal display device having the same, and manufacturing method thereof

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- Number: US 7,746,444 B2
- Document ID: US7746444B2
- Status: Granted
- Kind: B2
- Application number: 11/802,537
- Filed: 2007-05-23
- Published: 2007-12-27
- Granted: 2010-06-29
- Earliest claimed: 2006-06-26
- Assignees: LG Display Co., Ltd.
- Inventors: Jin Wuk Kim; Sang Yeup Lee
- Web page: https://patentgrep.com/patent/US7746444B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/134318: {having a patterned common electrode}
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

Provided is an array substrate, an LCD device having the same, and a manufacturing method thereof using IPP. The method includes forming a gate line and a gate electrode on a substrate using a first mold, forming a gate insulating layer over the substrate and the gate line, forming a first plane layer on first portions of the gate insulating layer, forming a semiconductor layer on second portions of the gate insulating layer using a second mold, forming a second plane layer over the first plane layer, forming a data line on the second plane layer and a source electrode and a drain electrode on the semiconductor layer using a third mold, forming a passivation layer having a contact hole using a fourth mold, and forming a pixel electrode on the passivation layer using a fifth mold, the pixel electrode electrically connected to the drain electrode via the contact hole.

## Claims

### Claim 1

A method for manufacturing an array substrate, the method comprising:
forming a gate line, a gate electrode and a common line on a substrate using a first mold;
forming a gate insulating layer over the substrate including the gate line, the gate electrode and the common line;
forming a first plane layer on first portions of the gate insulating layer;
forming a semiconductor layer on second portions of the gate insulating layer using a second mold;
forming a second plane layer over the first plane layer;
forming a data line on the second plane layer and a source electrode and a drain electrode on the semiconductor layer using a third mold;
forming a passivation layer having first and second contact holes using a fourth mold; and
forming a pixel electrode on the passivation layer using a fifth mold, the pixel electrode electrically connected to the drain electrode via the first contact hole.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the forming the first plane layer includes:
depositing a first material over the gate insulating layer; and
planarizing the deposited first material to expose the second portions of the gate insulating layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the forming the second plane layer includes:
depositing a second material over the first plane layer and the semiconductor layer; and
planarizing the deposited second material to expose the semiconductor layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the forming the gate line, the gate electrode and the common line includes using an in-plane printing process.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the forming the semiconductor layer includes using an in-plane printing process.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the forming the data line, the source electrode and the drain electrode includes using an in-plane printing process.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising forming a common electrode on the passivation layer using the fifth mold, the common electrode electrically connected to the common line via the second contact hole.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the common electrode includes a plurality of common electrode protrusions, the common electrode protrusions extending from the common electrode.

### Claim 9 (depends on 7)

The method according to claim 7, wherein the forming the pixel electrode and the common electrode on the passivation layer includes using an in-plane printing process.

### Claim 10 (depends on 7)

The method according to claim 7, wherein the forming of the common electrode includes:
forming a transparent conductive material on the passivation layer;
forming a fourth etching resist pattern on the transparent conductive material using the fifth mold; and
patterning the transparent conductive material using the fourth etching resist pattern.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the pixel electrode includes a plurality of pixel electrode protrusions, the pixel electrode protrusions extending from the pixel electrode.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the forming the passivation layer having the first and second contact holes includes using an in-plane printing process.

### Claim 13 (depends on 1)

The method according to claim 1, wherein the first plane layer is formed of one of an organic insulating material and an inorganic insulating material.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the first plane layer is formed of a material the same as the gate insulating layer.

### Claim 15 (depends on 1)

The method according to claim 1, wherein the first plane layer and the gate insulating layer include different materials.

### Claim 16 (depends on 1)

The method according to claim 1, wherein the second plane layer is formed of a material the same as the first plane layer.

### Claim 17 (depends on 1)

The method according to claim 1, wherein the first plane layer and the second plane layer include different materials.

### Claim 18 (depends on 1)

The method according to claim 1, wherein the forming of the gate line, the gate electrode and the common line includes:
forming a first metal film on the substrate;
forming a first etching resist pattern on the first metal film using the first mold; and
patterning the first metal film using the first etching resist pattern.

### Claim 19 (depends on 18)

The method according to claim 18, wherein a thickness of a pattern of the first mold is greater than a thickness of the first etching resist pattern.

### Claim 20 (depends on 18)

The method according to claim 18, wherein the first etching resist pattern is formed of a resist material having a surface energy difference greater than the first mold.

### Claim 21 (depends on 20)

The method according to claim 20, wherein the resist material includes one of polyethylene glycol, hexandiol diacylate, and 1,4-butanediol diglycidyl ether.

### Claim 22 (depends on 1)

The method according to claim 1, wherein the forming of the semiconductor layer includes:
forming a semiconductor material on the gate insulating layer and the first plane layer;
forming a second etching resist pattern on the semiconductor material using the second mold; and
patterning the semiconductor material using the second etching resist pattern.

### Claim 23 (depends on 22)

The method according to claim 22, wherein a thickness of a pattern of the second mold is greater than a thickness of the second etching resist pattern.

### Claim 24 (depends on 22)

The method according to claim 22, wherein the second etching resist pattern is formed of a resist material having a surface energy difference greater than the second mold.

### Claim 25 (depends on 24)

The method according to claim 24, wherein the resist material includes one of polyethylene glycol, hexandiol diacylate, and 1,4-butanediol diglycidyl ether.

### Claim 26 (depends on 1)

The method according to claim 1, wherein the forming of the data line, the source electrode and the drain electrode includes:
forming a second metal film on the semiconductor layer and the second plane layer;
forming a third etching resist pattern on the second metal film using the third mold; and
patterning the second metal film using the third etching resist pattern.

### Claim 27 (depends on 26)

The method according to claim 26, wherein a thickness of a pattern of the third mold is greater than a thickness of the third etching resist pattern.

### Claim 28 (depends on 26)

The method according to claim 26, wherein the third etching resist pattern is formed of a resist material having a surface energy difference greater than the third mold.

### Claim 29 (depends on 28)

The method according to claim 28, wherein the resist material includes one of polyethylene glycol, hexandiol diacylate, and 1,4-butanediol diglycidyl ether.

### Claim 30 (depends on 1)

The method according to claim 1, wherein the forming of the passivation layer having the first and second contact holes includes:
forming an insulating material on the second plane layer;
forming the first contact hole exposing the drain electrode and a hole portion using the fourth mold; and
patterning the first and the second plane layers through the hole portion to form the second contact hole exposing the common line.

### Claim 31 (depends on 1)

The method according to claim 1, wherein the forming of the pixel electrode includes:
forming a transparent conductive material on the passivation layer;
forming a fourth etching resist pattern on the transparent conductive material using the fifth mold; and
patterning the transparent conductive material using the fourth etching resist pattern.

### Claim 32 (depends on 31)

The method according to claim 31, wherein a thickness of a pattern of the fifth mold is greater than a thickness of the fourth etching resist pattern.

### Claim 33 (depends on 31)

The method according to claim 31, wherein the fourth etching resist pattern is formed of a resist material having a surface energy difference greater than the fifth mold.

### Claim 34 (depends on 33)

The method according to claim 33, wherein the resist material includes polyethylene glycol, hexandiol diacylate, and 1,4-butanediol diglycidyl ether.

### Claim 35 (depends on 1)

The method according to claim 1, wherein the first plane layer is formed on the first portions of the gate insulating layer that does not correspond to the gate line, the gate electrode and the common line.