# US 7,746,416 B2 · Pixel array substrate having storage capacitances that vary along a scan line > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,416 B2 - Document ID: US7746416B2 - Status: Granted - Kind: B2 - Application number: 11/365,262 - Filed: 2006-03-01 - Published: 2006-09-07 - Granted: 2010-06-29 - Earliest claimed: 2005-03-02 - Assignees: Chimei Innolux Corporation - Inventors: Yuan-Liang Wu - Web page: https://patentgrep.com/patent/US7746416B2 ## CPC - G02F 1/136213: {Storage capacitors associated with the pixel electrode} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 2300/0426: Layout of electrodes and connections - G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device has a pixel array substrate that contains a support substrate and a plurality of pixel areas arranged on the support substrate. Each pixel area contains a pixel electrode and a capacitor electrode. Scan lines and common lines are also provided, where each common line has portions provided in respective pixel areas. Each pixel area has a storage capacitance defined by an overlapping area between a respective capacitor electrode and a respective one of a scan line and common line, where the storage capacitances of pixel areas along each scan line varies along the scan line. ## Claims ### Claim 1 A pixel array substrate, comprising: a support substrate; a first conductor layer, a second conductor layer, and a third conductor layer, the first, second, and third conductor layers on said support substrate; a plurality of pixel areas arranged on the support substrate, wherein each pixel area contains a pixel electrode that is part of said third conductor layer, and a capacitor electrode that is part of said second conductor layer; and scan lines and common lines that are part of said first conductor layer, wherein each common line has portions provided in respective pixel areas, wherein each pixel area has a storage capacitance defined by an overlapping area between the respective capacitor electrode and a respective one of the scan line and the common line, wherein the storage capacitances of pixel areas along each scan line varies with increasing distance from a first end of each scan line, and wherein the first conductor layer and second conductor layer are formed of metal that is electrically conductive and non-transparent. ### Claim 2 (depends on 1) The pixel array substrate of claim 1, further comprising a scan line driving circuit to drive the scan lines, wherein the first ends of respective scan lines are connected to the scan line driving circuit. ### Claim 3 (depends on 1) The pixel array substrate of claim 1, wherein the storage capacitances of the pixel areas along a particular one of the scan lines decreases with increasing distance from the first end of the particular scan line. ### Claim 4 (depends on 3) The pixel array substrate of claim 3, wherein the decreasing storage capacitances of the pixel areas along the particular scan line enable substantially identical feed-through voltage effect in all of the pixel areas along the particular scan line. ### Claim 5 (depends on 1) The pixel array substrate of claim 1, wherein apertures of the pixel areas remain substantially identical even though the storage capacitances are varied. ### Claim 6 (depends on 1) The pixel array substrate of claim 1, wherein the storage capacitances of pixel areas are varied by varying areas of respective capacitor electrodes. ### Claim 7 (depends on 1) The pixel array substrate of claim 1, wherein the storage capacitances of pixel areas are varied by varying widths of the portions of a corresponding common line in respective pixel areas. ### Claim 8 (depends on 1) The pixel array substrate of claim 1, wherein the storage capacitances of pixel areas are varied by varying areas of respective capacitor electrodes and varying widths of the portions of a corresponding common line in respective pixel areas. ### Claim 9 (depends on 1) The pixel array substrate of claim 1, wherein the storage capacitances are varied by varying distances between capacitor and the respective one of the scan line and common line. ### Claim 10 (depends on 1) The pixel array substrate of claim 1, which is adapted to be spaced apart from a counter substrate having a common electrode by a liquid crystal layer. ### Claim 11 (depends on 1) The pixel array substrate of claim 1, wherein the first, second, and third conductor layers are different layers. ### Claim 12 (depends on 1) The pixel array substrate of claim 1, wherein each pixel area further comprises an active component to enable provision of a voltage to a respective pixel electrode. ### Claim 13 (depends on 1) The pixel array substrate of claim 1, wherein each capacitor electrode is electrically contacted to a respective pixel electrode. ### Claim 14 (depends on 1) The pixel array substrate of claim 1, wherein the capacitor electrodes are provided above and overlap the common lines. ### Claim 15 (depends on 1) The pixel array substrate of claim 1, wherein the common lines are generally parallel to the scan lines. ### Claim 16 (depends on 1) The pixel array substrate of claim 1, wherein the capacitor electrodes are provided above and overlap the scan lines. ### Claim 17 A liquid crystal display (LCD) device, comprising: a counter substrate having a common electrode; a pixel away substrate; and a liquid crystal layer between the counter substrate and the pixel array substrate, wherein the pixel away substrate comprises: a support substrate; a first conductor layer, a second conductor layer, and a third conductor layer, the first, second, and third conductor layers on the support substrate; a plurality of pixel areas arranged on the support substrate, wherein each pixel area contains a pixel electrode and a capacitor electrode, wherein the pixel electrodes are part of the third conductor layer, and the capacitor electrodes are p art of the second conductor layer; and scan lines and common lines that are part of the first conductor layer, wherein each common line has portions provided in respective pixel areas, wherein each pixel area has a storage capacitance defined by an overlapping area between the respective capacitor electrode and a respective one of the scan line and common line, wherein the storage capacitances of pixel areas along each scan line varies along the scan line, and wherein the first conductor layer and second conductor layer are formed of metal that is electrically conductive and non-transparent. ### Claim 18 (depends on 17) The LCD device of claim 17, wherein the pixel array substrate further comprises a scan line driving circuit to drive the scan lines, and wherein first ends of the scan lines are connected to the scan line driving circuit, and wherein the storage capacitances of the pixel areas along a particular one of the scan lines decreases with increasing distance from the first end of the particular scan line. ### Claim 19 (depends on 17) The LCD device of claim 17, wherein the storage capacitances are varied by varying areas of the capacitor electrodes. ### Claim 20 (depends on 19) The LCD device of claim 19, wherein a particular scan line or common line has a width, and wherein the capacitor electrodes overlapping the particular scan line or common line are contained entirely within the width of the particular scan line or common line such that varying the areas of the capacitor electrodes does not vary apertures of respective pixel areas. ### Claim 21 (depends on 17) The LCD device of claim 17, wherein the storage capacitances of a particular row are varied by varying widths of the portions of a particular common line, and wherein the capacitor electrodes in the particular row have substantially identical widths such that respective portions of the particular common line are contained entirely within the widths of respective capacitor electrodes. ### Claim 22 (depends on 17) The LCD device of claim 17, further comprising a backlight module to provide light to the liquid crystal layer. ### Claim 23 A method of making a display device having a pixel away substrate, the pixel away substrate having first, second, and third conductor layers and having pixel areas, each pixel area having a respective capacitor electrode and a second electrode, the method comprising: forming storage capacitances in respective pixel areas, wherein each storage capacitance is formed by overlapping a capacitor electrode with a second electrode in the corresponding pixel area, wherein the capacitor electrodes are part of the second conductor layer, wherein the pixel areas further comprise pixel electrodes that are part of the third conductor layer that is different from the second conductor layer, and wherein the second electrode is part of the first conductor layer that is different from the second and third conductor layers; and varying the storage capacitances along each of plural scan lines by varying areas of overlap between the capacitor electrodes and the second electrodes. ### Claim 24 (depends on 23) The method of claim 23, wherein a first end of each scan line is connected to a scan line driving circuit, and wherein varying the storage capacitances along each of the scan lines comprises reducing the storage capacitances with increasing distance from the first end of each scan line. ### Claim 25 (depends on 23) The method of claim 23, wherein the second electrodes comprise portions of the scan lines. ### Claim 26 (depends on 23) The method of claim 23, wherein the second electrodes comprise portions of common lines. ### Claim 27 (depends on 23) The method of claim 23, further comprising: arranging the pixel array substrate in a display device also having a counter substrate and a liquid crystal layer, wherein the counter substrate has a common electrode, and the liquid crystal layer is between the pixel away substrate and the counter substrate. ### Claim 28 (depends on 23) The method of claim 23, further comprising electrically contacting each of the pixel electrodes to a corresponding one of the capacitor electrodes. ### Claim 29 (depends on 23) The method of claim 23, further comprising: arranging the second conductor layer between the first conductor layer and the third conductor layer. ### Claim 30 (depends on 23) The method of claim 23, further comprising forming each of the first and second conductor layers of metal that is non-transparent. ### Claim 31 (depends on 1) The pixel away substrate of claim 1, wherein the second conductor layer is between the first conductor layer and the third conductor layer. ### Claim 32 (depends on 17) The LCD device of claim 17, wherein each of the pixel electrodes is electrically contacted to a corresponding one of the capacitor electrodes. ### Claim 33 (depends on 17) The LCD device of claim 17, wherein the second conductor layer is between the first conductor layer and the third conductor layer.