# US 7,746,398 B2 · Wide dynamic range active pixel with knee response > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,398 B2 - Document ID: US7746398B2 - Status: Granted - Kind: B2 - Application number: 11/709,702 - Filed: 2007-02-23 - Published: 2007-07-12 - Granted: 2010-06-29 - Earliest claimed: 2003-05-08 - Assignees: Micron Technology, Inc. - Inventors: Isao Takayanagi - Web page: https://patentgrep.com/patent/US7746398B2 ## CPC - H04N 25/59: by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance - H04N 25/575: {with a response composed of multiple slopes} - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment a pixel circuit comprises a photoconversion device for accumulating charge during a first integration period and second integration period, an integration node connected to the photoconversion device, a first transistor having one terminal connected to said integration node and another terminal connected to a reset signal line and a feed-through pulse capacitor. The feed-through pulse capacitor has one terminal coupled to a feed-through pulse signal line, and a second terminal coupled to the integration node, said feed-through pulse signal line providing an intermediate pulse between the first and second integration periods to generate an overflow current in said the transistor. ## Claims ### Claim 1 A pixel circuit, comprising: a photoconversion device for accumulating charge during a first integration period and second integration period; an integration node, connected to said photoconversion device; a first transistor, having one terminal connected to said integration node and another terminal connected to a reset signal line; a feed-through pulse capacitor, having one terminal coupled to a feed-through pulse signal line, and a second terminal coupled to said integration node, said feed-through pulse signal line providing an intermediate pulse between said first and second integration periods to generate an overflow current in said first transistor. ### Claim 2 (depends on 1) The pixel circuit of claim 1, wherein said photoconversion device is a photodiode. ### Claim 3 (depends on 1) The pixel circuit of claim 1, wherein the first transistor has a gate coupled to a supply voltage. ### Claim 4 (depends on 1) The pixel circuit of claim 1, wherein said reset signal line and said feed-through pulse line are operable to apply a reset voltage to said integration node. ### Claim 5 (depends on 4) The pixel circuit of claim 4, further comprising an output circuit to read out said reset voltage to an output line. ### Claim 6 (depends on 1) The pixel circuit of claim 1, wherein a pixel select line coupled to the integration node, is operable to begin a first charge integration period. ### Claim 7 (depends on 6) The pixel circuit of claim 6, wherein said pixel select line is operable to begin a second charge integration period following said first integration period. ### Claim 8 An imaging device, comprising: a semiconductor substrate; an array of pixels formed on said substrate, each pixel having a pixel circuit comprising: a photoconversion device for accumulating a charge at an integration node; a transfer transistor, having one source/drain terminal connected to said integration node and another source/drain terminal connected to a reset line; an output circuit, connected to said integration node; and a feed-through pulse capacitor, having one terminal coupled to a feed-through pulse signal line, and a second terminal coupled to said integration node, said feed-through pulse signal line producing an intermediate pulse that interrupts a charge integration period to create a first charge integration period and a second charge integration period. ### Claim 9 (depends on 8) The imaging device of claim 8, wherein said transfer transistor produces overflow current between said first and second charge integration periods in response to said intermediate pulse. ### Claim 10 (depends on 8) The imaging device of claim 8, wherein said photoconversion device is a photodiode. ### Claim 11 (depends on 8) The imaging device of claim 8, wherein said transfer transistor has a gate coupled to a supply voltage. ### Claim 12 (depends on 8) The imaging device of claim 8, wherein said reset signal line and said feed-through pulse line are operable to apply a reset voltage to said integration node. ### Claim 13 (depends on 12) The imaging device of claim 12, wherein said output circuit reads out said reset voltage to an output line. ### Claim 14 An imaging system, comprising: a plurality of pixels arranged in rows and columns, each pixel being associated with a column line, each pixel having a pixel circuit comprising: a photodiode for accumulating charge during a first integration period and second integration period, said device being connected to an integration node; a first transistor, having one terminal connected to said integration node and another terminal connected to a reset line; an output circuit, connected to said integration node, for reading out a signal at said integration node; and a feed-through pulse capacitor, having one terminal coupled to a feed-through pulse signal line, and a second terminal coupled to said integration node; wherein an excess charge overflows through said first transistor in response to an intermediate pulse generated by said feed-through pulse signal line. ### Claim 15 (depends on 14) The imaging system of claim 14, wherein said excess charge overflows when a photocurrent present at said integration node after said first integration period exceeds a predetermined threshold. ### Claim 16 (depends on 14) The imaging system of claim 14, wherein the first transistor has a gate coupled to a supply voltage. ### Claim 17 (depends on 14) The imaging system of claim 14, wherein said reset signal line and said feed-through pulse line are operable to apply a reset voltage to said integration node. ### Claim 18 (depends on 17) The imaging system of claim 17, wherein said output circuit further comprises a second transistor for reading out said reset voltage to an output line.