# US 7,746,348 B2 · Multi-thread graphics processing system

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- Number: US 7,746,348 B2
- Document ID: US7746348B2
- Status: Granted
- Kind: B2
- Application number: 11/746,427
- Filed: 2007-05-09
- Published: 2007-09-27
- Granted: 2010-06-29
- Earliest claimed: 2003-09-29
- Assignees: ATI Technologies ULC
- Inventors: Laurent Lefebvre; Andrew E. Gruber; Stephen L. Morein
- Web page: https://patentgrep.com/patent/US7746348B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06T 1/60: Memory management
- G06T 15/005: {General purpose rendering architectures}
- G06T 15/04: Texture mapping
- G09G 5/001: {Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor}
- G09G 5/363: {Graphics controllers}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.

## Claims

### Claim 1

A graphics processing system comprising:
a single arithmetic logic unit operable to execute a command thread selected from either of at least one pixel command thread and at least one vertex command thread;
an arbiter, coupled to the single arithmetic logic unit, operable to select the command thread from either of the at least one pixel command thread and the at least one vertex command thread and provide the command thread to the single arithmetic logic unit;
a renderer coupled to the single arithmetic logic unit; and
a scan converter coupled to the single arithmetic logic unit.

### Claim 2 (depends on 1)

The graphics processing system of claim 1, wherein the single arithmetic logic unit is further operative to complete processing of a pixel command thread of the at least one pixel command thread to provide an executed command thread, and to provide the executed command thread to the renderer.

### Claim 3 (depends on 1)

The graphics processing system of claim 1, wherein the single arithmetic logic unit is further operative to complete processing of a vertex command thread of the at least one vertex command thread to provide an executed command thread, and to provide the executed command thread to the scan converter.

### Claim 4 (depends on 1)

The graphics processing system of claim 1, further comprising:
at least one memory device in communication with the arbiter, the at least one memory device comprising a first portion operative to store the at least one pixel command thread and a second portion operative to store the at least one vertex command thread.

### Claim 5 (depends on 4)

The graphics processing system of claim 4, wherein the at least one memory device comprises at least one multi-port memory device and at least one one-port memory device.

### Claim 6 (depends on 4)

The graphics processing system of claim 4, wherein the at least one memory device comprises at least one register.

### Claim 7 (depends on 4)

The graphics processing system of claim 4, further comprising:
an input command arbiter, in communication with the at least one memory device, operative to provide the at least one pixel command thread to the first portion of the at least one memory device and to provide the at least one vertex command thread to the second portion of the at least one memory device.

### Claim 8 (depends on 1)

The graphics processing system of claim 1, wherein the single arithmetic logic unit is further operative to complete processing of the command thread to provide an executed command thread, and provide the executed command thread to either of the renderer or the scan converter.

### Claim 9

A method for command processing comprising:
selecting, by an arbiter coupled to a single arithmetic logic unit, the command thread from either of at least one pixel command thread and at least one vertex command thread;
receiving, by the single arithmetic logic unit from the arbiter, the command thread; and
providing, by the single arithmetic logic unit upon completion of the command thread, an executed command thread to either of a renderer and a scan converter coupled to the single arithmetic logic unit.

### Claim 10 (depends on 9)

The method of claim 9, wherein selecting the command thread by the arbiter further comprises selecting the command thread from either of a first portion or a second portion of at least one memory coupled to the arbiter, the first portion storing the at least one pixel command thread and the second portion storing the at least one vertex command thread.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
providing, by an input command arbiter in communication with the at least one memory device, the at least one pixel command thread to the first portion of the at least one memory device and the at least one vertex command thread to the second portion of the at least one memory device.

### Claim 12

A method for command processing comprising:
selecting, by an arbiter coupled to a single arithmetic logic unit, a pixel command thread from at least one pixel command thread;
receiving, by the single arithmetic logic unit, the pixel command thread;
providing, by the single arithmetic logic unit upon completion of the pixel command thread, an executed command thread to a renderer coupled to the single arithmetic logic unit;
selecting, by the arbiter, a vertex command thread from at least one pixel command thread;
receiving, by the single arithmetic logic unit, the vertex command thread; and
providing, by the single arithmetic logic unit upon completion of the vertex command thread, another executed command thread to a scan converter coupled to the single arithmetic logic unit.