# US 7,746,337 B2 · Inverter circuit

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- Number: US 7,746,337 B2
- Document ID: US7746337B2
- Status: Granted
- Kind: B2
- Application number: 11/450,770
- Filed: 2006-06-09
- Published: 2007-05-17
- Granted: 2010-06-29
- Earliest claimed: 2005-11-17
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Tatsuhisa Shimura; Takashi Kinoshita; Osamu Sengoku
- Web page: https://patentgrep.com/patent/US7746337B2

## CPC

- H02M 7/538: in a push-pull configuration (H02M7/5375 takes precedence {; with oscillating arrangements H02M7/53832, H02M7/53846})
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H03K 17/691: using transformer coupling
- H05B 41/2828: {using control circuits for the switching elements (H05B41/2827 takes precedence)}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL

## Abstract

An inverter circuit includes a first driving transformer, a second driving transformer, a power voltage circuit, a high-side FET connected to a secondary winding of the first driving transformer, a low-side FET connected to a secondary winding of the second driving transformer and an inverter transformer connected to a driving node between the high-side FET and the low-side FET. Thus, a direct current path does not exist between a gate of the high-side FET and the driving node, so that a gate voltage of the high-side FET is biased more to a negative polarity.

## Claims

### Claim 1

An inverter circuit comprising:
a first transformer having a primary winding to which a first control signal is applied;
a second transformer having a primary winding to which a second control signal is applied;
a power voltage circuit to generate a predetermined direct current voltage;
a first field effect transistor electrically connected between the power voltage circuit and a driving node, the first field effect transistor having a gate connected to a secondary winding of the first transformer;
a second field effect transistor electrically connected between the driving node and a ground, the second field effect transistor having a gate connected to a secondary winding of the second transformer; and
a third transformer electrically connected to the driving node,
wherein a voltage level applied to the gate of the first field effect transistor is maintained in a minus voltage level compared to a voltage level at the driving node during one cycle of the first control signal such that no direct current path exists between the gate of the first field effect transistor and the driving node.

### Claim 2 (depends on 1)

The inverter circuit of claim 1, wherein an absolute value of the minus voltage level increases as a pulse width of the first control signal increases.

### Claim 3 (depends on 2)

The inverter circuit of claim 2, further comprising:
a first impedance converting circuit and a first resistor connected in series between the secondary winding of the first transformer and the gate of the first field effect transistor, the first impedance converting circuit making an impedance of the first transformer lower than an impedance of the first resistor; and
a second impedance converting circuit and a second resistor connected in series between the secondary winding of the second transformer and the gate of the second field effect transistor, the second impedance converting circuit making an impedance of the second transformer lower than an impedance of the second resistor.

### Claim 4 (depends on 3)

The inverter circuit of claim 3, wherein the first impedance converting circuit is a push-pull circuit having a first impedance converting transistor and a second impedance converting transistor connected to each other in series, and input terminals of the first and second impedance converting transistors are driven by the secondary winding of the first transformer.

### Claim 5 (depends on 3)

The inverter circuit of claim 3, further comprising diodes each connected in parallel to a respective one of the first and second resistors.

### Claim 6 (depends on 1)

The inverter circuit of claim 1, further comprising a capacitor electrically connected between a primary winding of the third transformer and the driving node.

### Claim 7 (depends on 6)

The inverter circuit of claim 6, further comprising:
a first impedance converting circuit and a first resistor connected in series between the secondary winding of the first transformer and the gate of the first field effect transistor, the first impedance converting circuit making an impedance of the first transformer lower than an impedance of the first resistor; and
a second impedance converting circuit and a second resistor connected in series between the secondary winding of the second transformer and the gate of the second field effect transistor, the second impedance converting circuit making an impedance of the second transformer lower than an impedance of the second resistor.

### Claim 8 (depends on 1)

The inverter circuit of claim 1, further comprising:
a first impedance converting circuit and a first resistor connected in series between the secondary winding of the first transformer and the gate of the first field effect transistor, the first impedance converting circuit making an impedance of the first transformer lower than an impedance of the first resistor; and
a second impedance converting circuit and a second resistor connected in series between the secondary winding of the second transformer and the gate of the second field effect transistor, the second impedance converting circuit making an impedance of the second transformer lower than an impedance of the second resistor.

### Claim 9 (depends on 8)

The inverter circuit of claim 8, wherein the first impedance converting circuit is a push-pull circuit having a first impedance converting transistor and a second impedance converting transistor connected to each other in series, and input terminals of the first and second impedance converting transistors are driven by the secondary winding of the first transformer.

### Claim 10 (depends on 8)

The inverter circuit of claim 8, further comprising diodes each connected in parallel to a respective one of the first and second resistors.

### Claim 11

An inverter circuit comprising:
a first transformer having a primary winding to which a first control signal is applied;
a second transformer having a primary winding to which a second control signal is applied;
a power voltage circuit to generate a predetermined direct current voltage;
a first field effect transistor electrically connected between the power voltage circuit and a driving node, the first field effect transistor having a gate connected to a secondary winding of the first transformer;
a second field effect transistor electrically connected between the driving node and a ground, the second field effect transistor having a gate connected to a secondary winding of the second transformer;
a third transformer electrically connected to the driving node; and
a first resistor electrically connected to the gate of the first field effect transistor,
wherein a first impedance converting circuit is connected between the secondary winding of the first transformer and the first resistor to reduce an impedance of the first resistor, which is viewed from the first transformer.

### Claim 12 (depends on 11)

The inverter circuit of claim 11, wherein the first impedance converting circuit is a push-pull circuit having a first impedance converting transistor and a second impedance converting transistor, and input terminals of the first and second impedance converting transistors are connected to the secondary winding of the first transformer.

### Claim 13 (depends on 12)

The inverter circuit of claim 12, wherein the first and second impedance converting transistors are driven by a bias voltage obtained by rectifying an alternating current signal from the secondary winding of the first transformer.

### Claim 14 (depends on 13)

The inverter circuit of claim 13, further comprising a diode and a capacitor to generate the bias voltage.

### Claim 15 (depends on 11)

The inverter circuit of claim 11, further comprising a diode electrically connected to the first resistor in parallel.

### Claim 16 (depends on 11)

The inverter circuit of claim 11, further comprising:
a second resistor electrically connected to the gate of the second field effect transistor; and
a second impedance converting circuit connected between the secondary winding of the second transformer and the second resistor to reduce an impedance of the second resistor, which is viewed from the second transformer.

### Claim 17 (depends on 16)

The inverter circuit of claim 16, wherein the first impedance converting circuit is a push-pull circuit having a first impedance converting transistor and a second impedance converting transistor, and input terminals of the first and second impedance converting transistors are connected to the secondary winding of the first transformer, and
the second impedance converting circuit is a push-pull circuit having a third impedance converting transistor and a fourth impedance converting transistor, and input terminals of the third and fourth impedance converting transistors are connected to the secondary winding of the second transformer.

### Claim 18 (depends on 17)

The inverter circuit of claim 17, wherein the first and second impedance converting transistors are driven by a first bias voltage obtained by rectifying an alternating current signal from the secondary winding of the first transformer, and the third and fourth impedance converting transistors are driven by a second bias voltage obtained by rectifying an alternating current signal from the secondary winding of the second transformer.

### Claim 19 (depends on 18)

The inverter circuit of claim 18, further comprising a diode and a capacitor to generate the first and second bias voltages.

### Claim 20 (depends on 16)

The inverter circuit of claim 16, further comprising:
a first diode electrically connected to the first resistor in parallel; and
a second diode electrically connected to the second resistor in parallel.

### Claim 21

A liquid crystal display comprising:
an inverter circuit to generate a power voltage;
a backlight assembly to generate light in response to the power voltage from the inverter circuit; and
a liquid crystal display panel that receives the light from the backlight assembly and image data to display an image,
the inverter circuit comprises:
a first transformer having a primary winding to which a first control signal is applied;
a second transformer having a primary winding to which a second control signal is applied;
a power voltage circuit to generate a predetermined direct current voltage;
a first field effect transistor electrically connected between the power voltage circuit and a driving node, the first field effect transistor having a gate connected to a secondary winding of the first transformer;
a second field effect transistor electrically connected between the driving node and a ground, the second field effect transistor having a gate connected to a secondary winding of the second transformer; and
a third transformer electrically connected to the driving node,
wherein a voltage level applied to the gate of the first field effect transistor is maintained in a minus voltage level compared to a voltage level at the driving node during one cycle of the first control signal such that no direct current path exists between the gate of the first field effect transistor and the driving node.