# US 7,746,306 B2 · Display device having an improved video signal drive circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,306 B2 - Document ID: US7746306B2 - Status: Granted - Kind: B2 - Application number: 11/753,942 - Filed: 2007-05-25 - Published: 2007-10-04 - Granted: 2010-06-29 - Earliest claimed: 2001-05-25 - Assignees: Hitachi, Ltd. - Inventors: Toshio Miyazawa - Web page: https://patentgrep.com/patent/US7746306B2 ## CPC - G09G 3/2011: {by amplitude modulation} - G09G 3/3688: {suitable for active matrices only} - G09G 3/3685: {Details of drivers for data electrodes} - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device including: a plurality of pixels arranged in a matrix array; a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, wherein said video signal supplying circuit is provided with a transfer-data processing section for generating a data signal at a time assigned to a gray scale level, in accordance with n-bit data information representing said gray scale level, and a gray-scale voltage selector circuit section for supplying as said video signal, a voltage signal selected from among a plurality of gray-scale voltages, based upon said time associated with said data signal, said plurality of gray-scale voltages being successively selected. ## Claims ### Claim 1 A display device comprising: a plurality of pixels arranged in a matrix array; a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit including: a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3; a transfer-data processing section for generating a data signal at a time assigned to one of a plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section; a gray-scale voltage generator for generating a plurality of gray-scale voltages corresponding to said plurality of gray scale levels, respectively; and a gray-scale voltage selector circuit section in which individual said gray-scale voltages are successively-selected within one horizontal period, the gray-scale voltage selector circuit section adapted to select and output as said video signal, a voltage signal selected from among the successively-selected said plurality of gray-scale voltages, based upon said time associated with said data signal; wherein each of said plurality of gray-scale voltages are transferred through one of a plurality of gray-scale voltage lines, wherein said plurality of gray-scale signal voltage lines are common to all pixels in said selected row, and wherein each gray-scale voltage is constant during one horizontal period. ### Claim 2 (depends on 1) A display device according to claim 1, wherein said gray-scale voltage selector circuit section supplies as said video signal, said voltage signal selected from among said plurality of gray-scale voltages, by time coincidence between said gray scale level by successive selection of a plurality of gate lines each coupled to a switching circuit associated with one of said plurality of gray-scale voltages and said data signal supplied to said switching circuit from said transfer-data processing section. ### Claim 3 (depends on 1) A display device according to claim 1, wherein said transfer-data processing section generates said data signal at a time assigned to one of said plurality of gray scale levels represented by said n-bit data information, in synchronism with a clock waveform supplied to said transfer-data processing section; said gray-scale voltage selector circuit section successively attempts to select said plurality of gray-scale voltages corresponding to said plurality of gray scale levels, respectively, in synchronism with said clock waveform, and wherein said gray-scale voltage selector circuit section outputs as said video signal, one of said plurality of gray-scale voltages selected from said successively selected gray-scale voltages at said time associated with said data signal. ### Claim 4 (depends on 1) A display device according to claim 1, wherein said transfer-data processing section generates said data signal at a time assigned to one of said plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, in synchronism with a clock waveform supplied to said transfer-data processing section; a selection gate circuit successively generates a plurality of gate pulses associated with said plurality of gray-scale voltages, respectively, in synchronism with said clock waveform; and said gray-scale voltage selector circuit section successively attempts to select said plurality of gray-scale voltages, in synchronism with said gate pulses, and outputs as said video signal, one of said plurality of gray-scale voltages selected from said successively selected gray-scale voltages at said time associated with said data signal. ### Claim 5 A display device comprising: a plurality of pixels arranged in a matrix array; a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit including: a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3; a transfer-data processing section for generating a voltage-selecting timing signal corresponding in time to a time assigned to one of a plurality of gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, where the plurality of gray-scale levels are assigned to mutually different timings from each other; a gray-scale voltage generator for generating a plurality of gray-scale voltages corresponding to said plurality of gray scale levels, respectively; and a gray-scale voltage selector circuit section in which individual said gray-scale voltages are successively-selectable within one horizontal period, the gray-scale voltage selector circuit section adapted to select and output as said video signal, a voltage signal selected from among the successively-selectable said plurality of gray-scale voltages, based upon a time defined by said voltage-selecting timing signal; wherein each of said plurality of gray-scale voltages are transferred through one of a plurality of gray-scale signal voltage lines, wherein said plurality of gray-scale signal voltage lines are common to all pixels in said selected row, and wherein each gray-scale voltage is constant during one horizontal period. ### Claim 6 A display device comprising: a plurality of pixels arranged in a matrix array; a selector circuit for selecting one row of pixels from a plurality of rows of pixels in said matrix array; and a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, said video signal supplying circuit including: a digital data store section for storing n-bit data information for each of said plurality of pixels, n being an integer equal to or greater than 3; a transfer-data processing section for generating a voltage-selecting timing signal corresponding in time to a time assigned to one of a plurality of constant gray scale levels represented by said n-bit data information, in accordance with an output from said digital data store section, where the plurality of constant gray-scale levels are concurrently-generated onto a plurality of gray-scale signal voltage lines, respectively, and commonly-shared by all pixels in said selected row, and where the plurality of constant gray-scale levels are assigned to be selectable at mutually different timings of said voltage-selecting timing signal from each other; a gray-scale voltage generator for concurrently generating each of a plurality of constant gray-scale voltages corresponding to said plurality of constant gray scale levels, respectively; and a gray-scale voltage selector circuit section in which individual said constant gray-scale voltages provided on said plurality of gray-scale signal voltage lines are successively-selectable within one horizontal period, the gray-scale voltage selector circuit section adapted to select and output as said video signal, a voltage signal selected from among the successively-selectable said plurality of constant gray-scale voltages, based upon a time defined by said voltage-selecting timing signal.