# US 7,746,262 B2 · Coding method for digital to analog converter of a SAR analog to digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,262 B2 - Document ID: US7746262B2 - Status: Granted - Kind: B2 - Application number: 11/311,509 - Filed: 2005-12-19 - Published: 2007-06-21 - Granted: 2010-06-29 - Earliest claimed: 2005-12-19 - Assignees: Silicon Laboratories Inc. - Inventors: Golam R. Chowdhury; Douglas S. Piasecki; Bruce Del Signore; Kevin Kwak - Web page: https://patentgrep.com/patent/US7746262B2 ## CPC - H03M 1/462: {Details of the control circuitry, e.g. of the successive approximation register} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M 1/682: {both converters being of the unary decoded type} - H03M 1/687: {Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground. ## Claims ### Claim 1 A method for coding successive approximation register analog to digital converter, comprising the steps of: (a) switching capacitors associated with a bit from ground to a reference voltage; (b) determining whether a logical value of the bit is a first value or a second value; (c) if the logical value is the first value, switching capacitors associated with a next bit from the ground to the reference voltage; and (d) if the logical value is the second value, switching one-half of the capacitors associated with the bit currently connected to the reference voltage to ground. ### Claim 2 (depends on 1) The method of claim 1, further including the step of repeating steps (b)-(d) for each bit of the successive approximation register analog to digital converter. ### Claim 3 (depends on 1) The method of claim 1, further including the step of determining if the successive approximation register analog to digital converter is in a sampling mode or a conversion mode. ### Claim 4 (depends on 1) The method of claim 1, further including the steps of: repeating steps (b)-(d) for a first portion of the plurality of bits; and determining a value for a second portion of the plurality of bits using a binary coding technique. ### Claim 5 (depends on 1) The method of claim 1, further including the steps of: repeating steps (b)-(d) for each most significant bit of the plurality of bits; and repeating steps (b)-(d) for each least significant bit of the plurality of bits. ### Claim 6 A method for coding a successive approximation register analog to digital converter, comprising the steps of: sampling an input voltage; determining bit values for a first portion of a plurality of bits representing an output of the successive approximation register analog to digital converter using a thermometer coding technique, wherein the step of determining the bit values for a first portion of the plurality of bits further comprises the steps of: (a) switching capacitors associated with a bit from ground to a reference voltage; (b) determining whether a logical value of the bit is a first value or a second value; (c) if the logical value is the first value, switching capacitors associated with a next bit from the ground to the reference voltage; and (d) if the logical value is the second value, switching one-half of the capacitors associated with the bit currently connected to the reference voltage to ground; and determining bit values for a second portion of the plurality of bits representing the output of the successive approximation register analog to digital converter using a binary coding technique. ### Claim 7 (depends on 6) The method of claim 6, further including the step of repeating steps (b)-(d) for each bit of the first portion of the plurality of bits. ### Claim 8 (depends on 6) The method of claim 6, further including the step of determining if the successive approximation register analog to digital converter is in a sampling mode or a conversion mode. ### Claim 9 A method for coding a successive approximation register analog to digital converter, comprising the steps of: sampling an input voltage; determining bit values for each most significant bit of a plurality of bits representing an output of the successive approximation register analog to digital converter using a thermometer coding technique; determining bit values for each least significant bit of the plurality of bits representing the output of the successive approximation register analog to digital converter using the thermometer coding technique; and wherein transient errors are reduced since only one single switch is operated with respect to each bit value decision rather than two sets of switches generating transient noise to comparator inputs. ### Claim 10 (depends on 9) The method of claim 9, wherein the step of determining the bit values for each most significant bit of the plurality of bits further comprises the steps of: (a) switching capacitors associated with a bit from ground to a reference voltage; (b) determining whether a logical value of the bit is a first value or a second value; (c) if the logical value is the first value, switching capacitors associated with a next bit from the ground to the reference voltage; and (d) if the logical value is the second value, switching one-half of the capacitors associated with the bit currently connected to the reference voltage to ground. ### Claim 11 (depends on 10) The method of claim 10, further including the step of repeating steps (b)-(d) for each bit of the most significant bits of the plurality of bits. ### Claim 12 (depends on 9) The method of claim 9, wherein the step of determining the bit values for each least significant bit of the plurality of bits further comprises the steps of: (a) switching capacitors associated with a bit from ground to a reference voltage; (b) determining whether a logical value of the bit is a first value or a second value; (c) if the logical value is the first value, switching capacitors associated with a next bit from the ground to the reference voltage; and (d) if the logical value is the second value, switching one-half of the capacitors associated with the bit currently connected to the reference voltage to ground. ### Claim 13 (depends on 12) The method of claim 12, further including the step of repeating steps (b)-(d) for each bit of the least significant bits of the plurality of bits. ### Claim 14 (depends on 9) The method of claim 9, further including the step of determining if the successive approximation register analog to digital converter is in a sampling mode or a conversion mode. ### Claim 15 A successive approximation register analog to digital converter, comprising: a voltage comparator having first and second inputs and an output; a plurality of capacitors associated with a first group of bits connected to a first input of the voltage comparator, each of the capacitors having substantially a same value, a number of capacitors associated with each of the first group of bits doubling from a least significant bit of the first group of bits to a most significant bit of the first group of bit; and a controller configured to: (a) switch the capacitors associated with a bit from ground to a reference voltage; (b) determine whether a logical value of the bit is a first value or a second value; (c) if the logical value is the first value, switch capacitors associated with a next bit from the ground to the reference voltage; and (d) if the logical value is the second value, switch one-half of the capacitors associated with the bit currently connected to the reference voltage to ground. ### Claim 16 (depends on 15) The successive approximation register analog to digital converter of claim 15, wherein the controller is further configured to repeat steps (b)-(d) for each bit of the successive approximation register analog to digital converter. ### Claim 17 (depends on 15) The successive approximation register analog to digital converter of claim 15, wherein the controller is further configured to determine if the successive approximation register analog to digital converter is in a sampling mode or a conversion mode. ### Claim 18 (depends on 15) The successive approximation register analog to digital converter of claim 15, wherein the controller is further configured to: repeat steps (b)-(d) for a first portion of the plurality of bits; and determine a value for a second portion of the plurality of bits using a binary coding technique. ### Claim 19 (depends on 15) The successive approximation register analog to digital converter of claim 15, wherein the controller is further configured to: repeat steps (b)-(d) for each most significant bit of the plurality of bits; and repeat steps (b)-(d) for each least significant bit of the plurality of bits.