# US 7,746,257 B2 · Delta-sigma analog-to-digital converter circuit having reduced sampled reference noise > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,257 B2 - Document ID: US7746257B2 - Status: Granted - Kind: B2 - Application number: 12/366,214 - Filed: 2009-02-05 - Published: 2009-11-12 - Granted: 2010-06-29 - Earliest claimed: 2008-05-07 - Assignees: Cirrus Logic, Inc. - Inventors: Edmund M. Schneider; Eric J. Swanson; John L. Melanson - Web page: https://patentgrep.com/patent/US7746257B2 ## CPC - H03M 3/428: {with lower resolution, e.g. single bit, feedback} - H03M 3/368: {of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators} - H03M 3/414: {having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type} - H03M 3/456: {the modulator having a first order loop filter in the feedforward path} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A delta-sigma analog-to-digital converter (ADC) circuit improves performance by reducing the amount of noise and other error sampled by the reference switching circuit. The reference switching network is operated intermittently only when the charge on an input integrator exceeds a threshold, thereby preventing the input integrator from saturating, while avoiding needlessly injecting reference noise. The input to the ADC may be a current injected directly into a summing node of the integrator, or may be a voltage supplied through another switching network. ## Claims ### Claim 1 An analog-to-digital converter circuit, comprising: an integrator for receiving an input signal to be converted to a digital representation of the input signal; a reference switched-capacitor circuit for applying a reference charge to an input of the integrator to reduce a magnitude of a voltage of an output of the integrator, wherein the reference switched capacitor circuit is operated according to a switching clock; a comparison circuit for determining when the magnitude of the voltage of the output of the integrator exceeds a threshold voltage; and a control circuit for controlling switching of the reference switched-capacitor circuit in response to an output of the comparison circuit, wherein the switching clock is enabled in response to the magnitude of the voltage of the output of the integrator exceeding the threshold voltage. ### Claim 2 (depends on 1) The analog-to-digital converter circuit of claim 1, wherein the input signal is an input current coupled directly to an input summing node of the integrator. ### Claim 3 (depends on 1) The analog-to-digital converter circuit of claim 1, wherein the input signal is an input voltage, and further comprising an input switched-capacitor circuit for applying the input voltage to the integrator. ### Claim 4 (depends on 1) The analog-to-digital converter circuit of claim 1, further comprising a latch for latching the output of the comparison circuit according to a sampling clock, and wherein the control circuit enables switching of the reference switched-capacitor circuit in conformity with an output of the latch. ### Claim 5 (depends on 4) The analog-to-digital converter of claim 4, further comprising: an internal analog-to-digital converter having an input coupled to the output of the integrator for periodically generating output values according to the sampling clock; and a digital circuit for determining differences between the output values and to obtain the digital representation of the input signal in conformity with at least one of the differences and the state of the output of the latch. ### Claim 6 (depends on 1) The analog-to-digital converter of claim 1, further comprising: an internal analog-to-digital converter having an input coupled to the output of the integrator for periodically generating output values; and a digital circuit for determining differences between the output values to obtain the digital representation of the input signal. ### Claim 7 (depends on 6) The analog-to-digital converter of claim 6, wherein the digital circuit is a processor responsive to program instructions for computing the differences. ### Claim 8 A method of converting an analog signal level to a digital output value, comprising: continually integrating the analog signal level with an analog integrator; intermittently applying a reference charge to an input of the analog integrator to reduce a magnitude of a voltage of an output of the integrator according to a switching clock and a control indication that controls whether or not the switching clock applies the reference charge in a given period of the switching clock; determining when the magnitude of the voltage of the output of the integrator exceeds a threshold voltage; and generating the control indication in response to a result of the determining, wherein the switching clock applies the reference charge to the analog integrator in response to a result of the determining. ### Claim 9 (depends on 8) The method of claim 8, wherein the input signal is an input current, and further comprising providing the input current directly to an input summing node of the analog integrator. ### Claim 10 (depends on 8) The method of claim 8, wherein the input signal is an input voltage, and further comprising continuously applying the input voltage to the integrator through an input switched capacitor circuit according to the switching clock. ### Claim 11 (depends on 8) The method of claim 8, further comprising latching a result of the determining according to a sampling clock, and wherein the generating generates the control signal from a result of the latching. ### Claim 12 (depends on 11) The method of claim 11, further comprising: periodically generating output values according to the sampling clock from the output of the integrator using an analog-to-digital converter; and determining differences between the output values to obtain the digital representation of the input signal in conformity with at least one of the differences and a state of the result of the latching. ### Claim 13 (depends on 8) The method of claim 8, further comprising: periodically generating output values according to the sampling clock from the output of the integrator using an analog-to-digital converter; and determining differences between the output values to obtain the digital representation of the input signal in conformity with at least one of the differences. ### Claim 14 (depends on 13) The method of claim 13, wherein the determining is performed by computing the digital representation using a processor responsive to program instructions. ### Claim 15 An analog-to-digital converter circuit, comprising: an integrator for receiving an input signal to be converted to a digital representation of the input signal according to a sampling clock; a reference circuit for restoring the integrator toward a zero value output in order that the integrator remain in linear operation; and a control circuit for controlling operation of the reference circuit switching of the reference switched-capacitor circuit such that the reference circuit is not operated at each sampling clock but intermittently according to an indication of a magnitude of the output of the integrator. ### Claim 16 (depends on 15) The analog-to-digital converter of claim 15, wherein the control circuit comprises: a comparison circuit for comparing an output voltage of the integrator to a threshold voltage; and a latch for latching the output of the comparison circuit according to a sampling clock, and wherein the control circuit enables the reference circuit in conformity with an output of the latch. ### Claim 17 (depends on 16) The analog-to-digital converter of claim 16, further comprising: an internal analog-to-digital converter having an input coupled to the output of the integrator for periodically generating output values according to the sampling clock; and a digital circuit for determining differences between the output values and to obtain the digital representation of the input signal in conformity with at least one of the differences and the state of the output of the latch. ### Claim 18 A method of converting an analog signal level to digital output values, comprising: continually integrating the analog signal level with an analog integrator; restoring the analog integrator toward a zero value output in order that the analog integrator remain in linear operation; and determining when the magnitude of an output of the analog integrator exceeds a threshold voltage, wherein the restoring is performed only in response to the determining that the output of the analog integrator has exceeded the threshold voltage. ### Claim 19 (depends on 18) The method of claim 18, further comprising latching a result of the determining according to a sampling clock, and wherein the restoring is performed in conformity with a result of the latching. ### Claim 20 (depends on 19) The method of claim 19, further comprising: periodically generating the digital output values according to the sampling clock from the output of the integrator using an analog-to-digital converter; and determining differences between the output values to obtain the digital representation of the input signal in conformity with at least one of the differences and a state of the result of the latching.