# US 7,746,254 B2 · Sample and hold circuit, multiplying D/A converter having the same, and A/D converter having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,254 B2 - Document ID: US7746254B2 - Status: Granted - Kind: B2 - Application number: 12/318,201 - Filed: 2008-12-23 - Published: 2009-07-02 - Granted: 2010-06-29 - Earliest claimed: 2007-12-26 - Assignees: Denso Corporation - Inventors: Tetsuya Makihara; Masakiyo Horie - Web page: https://patentgrep.com/patent/US7746254B2 ## CPC - G11C 27/026: {associated with an amplifier (G11C27/028 takes precedence)} - H03M 1/129: {Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication} - H03M 1/0682: {using a differential network structure, i.e. symmetrical with respect to ground} - H03M 1/0695: {using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type} - H03M 1/403: {using switched capacitors} - H03M 1/442: {using switched capacitors} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is α, a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is β, a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is γ, and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is η. α is substantially different from β. A total capacitance of a feedback capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number. ## Claims ### Claim 1 A sample and hold circuit for sampling and holding an input voltage, the sample and hold circuit comprising: an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals; a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier; a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance; and a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η, wherein α is substantially different from β, and wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number. ### Claim 2 (depends on 1) The sample and hold circuit according to claim 1, wherein γ is substantially equal to η. ### Claim 3 (depends on 2) The sample and hold circuit according to claim 2, wherein α+β is substantially equal to γ+η. ### Claim 4 (depends on 1) The sample and hold circuit according to claim 1, wherein the input voltage is a differential input voltage comprising an inverting input voltage and a non-inverting input voltage, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as αp, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as βp, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as γp, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as ηp, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as αm, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as βm, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as γm, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as ηm, wherein αp is substantially different from βp, wherein αm is substantially different from βm, wherein αp−βp is substantially equal to αm-βm, and wherein the total capacitance of the at least one capacitor pair is substantially equal to (αp−βp−γp+ηp)·(N/2), where N is a positive number. ### Claim 5 (depends on 4) The sample and hold circuit according to claim 4, wherein γp is substantially equal to ηp, and wherein γm is substantially equal to ηm. ### Claim 6 (depends on 5) The sample and hold circuit according to claim 5, wherein αp+βp is substantially equal to γp+ηp, and wherein αm+βm is substantially equal to γm+ηm. ### Claim 7 (depends on 1) The sample and hold circuit according to claim 1, wherein the input voltage is a differential input voltage comprising an inverting input voltage and a non-inverting input voltage, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as αp, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as βp, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as γp, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as ηp, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as αm, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the sampling phase is defined as βm, wherein a total capacitance of the inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as γm, wherein a total capacitance of the non-inverting-side capacitors to which the non-inverting input voltage is applied in the holding phase is defined as ηm, wherein αp is substantially different from βp, wherein αm is substantially different from βm, wherein αp−βp is substantially equal to αm−βm, and wherein the total capacitance of the at least one capacitor pair is substantially equal to (αm−βm−γm+ηm)·(N/2), where N is a positive number. ### Claim 8 (depends on 1) The sample and hold circuit according to claim 1, wherein the control circuit causes the operational amplifier to serve as a voltage follower in the sampling phase to bias the inverting and non-inverting input terminals of the operational amplifier to a predetermined voltage. ### Claim 9 (depends on 1) The sample and hold circuit according to claim 1, wherein each of the inverting-side and non-inverting-side capacitors of the at least one capacitor pair has a variable capacitance. ### Claim 10 (depends on 1) A multiplying D/A converter comprising: an input terminal configured to receive a digital value; and the sample and hold circuit of claim 1, wherein in the sampling phase, the control circuit of the sample and hold circuit applies the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and a DAC voltage to at least one of the others of the plurality of inverting-side and non-inverting-side capacitors, and wherein the DAC voltage depends on the digital value. ### Claim 11 (depends on 10) An A/D converter comprising: an A/D conversion section configured to output an input digital value corresponding to a magnitude of the input voltage; a multiplying D/A converter of claim 10; and an unit conversion circuit configured to output a first residue voltage by doubling a difference between a D/A conversion value of the input digital value and a value obtained by multiplying the input voltage by 1/N, wherein an operation in which the first residue voltage is inputted to the unit conversion circuit to cause the unit conversion circuit to output a second residue voltage is repeated a predetermined number of times to produce an A/D conversion code of the input voltage. ### Claim 12 (depends on 11) The A/D converter according to claim 11, wherein the unit conversion circuit comprises a plurality of unit conversion circuits connected in series. ### Claim 13 (depends on 11) The A/D converter according to claim 11, wherein the unit conversion circuit comprises a single unit conversion circuit, and wherein the second residue voltage outputted from the unit conversion circuit is inputted to the unit conversion circuit as the first residue voltage. ### Claim 14 (depends on 11) The A/D converter according to claim 11, wherein the unit conversion circuit outputs the second residue voltage by doubling a difference between the D/A conversion value of the input digital value and the first residue voltage. ### Claim 15 A sample and hold circuit for sampling and holding an input voltage limited to a predetermined voltage range, the sample and hold circuit comprising: an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals; a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier; a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance; and a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η, wherein α+β is substantially equal to γ+η, wherein α+η is substantially different from β+γ, and wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number. ### Claim 16 A sample and hold circuit for sampling and holding an input voltage limited to a predetermined voltage range, the sample and hold circuit comprising: an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals; a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier; a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance; and a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η, wherein α+β is substantially equal to γ+η, wherein α is substantially different from γ, wherein β is substantially different from η, and wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.