# US 7,746,252 B2 · Analog front-end circuit and electronic instrument

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- Number: US 7,746,252 B2
- Document ID: US7746252B2
- Status: Granted
- Kind: B2
- Application number: 12/072,329
- Filed: 2008-02-26
- Published: 2008-08-28
- Granted: 2010-06-29
- Earliest claimed: 2007-02-27
- Assignees: Seiko Epson Corporation
- Inventors: Masahiko Mizuta
- Web page: https://patentgrep.com/patent/US7746252B2

## CPC

- H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An analog front-end circuit includes an analog processing circuit, an A/D converter, a target register in which a lower limit target value of an input image signal is set, and a calculation circuit. The analog processing circuit includes an offset control circuit which performs offset control based on an offset control value set in an offset control register. The calculation circuit monitors the A/D-converted value in a lower limit value output period when the A/D-converted value corresponding to a lower limit value of an input range is output from the A/D converter, and sets the offset control value that causes the A/D-converted value to become closer to the lower limit target value set in the target register in the offset control register.

## Claims

### Claim 1

An analog front-end circuit comprising:
an analog processing circuit that receives an input image signal from an image sensor, performs a given process on the input image signal, and outputs an image signal;
an A/D converter that A/D-converts the image signal input from the analog processing circuit and outputs an A/D converted value;
a target register, a lower limit target value of an input range of the image signal input from the analog processing circuit to the A/D converter being set in the target register; and
a calculation circuit that monitors the A/D-converted value output from the A/D converter and performs a calculation process,
the analog processing circuit including an offset control circuit that includes an offset control register and performs offset control on the input image signal to output the image signal based on an offset control value set in the offset control register; and
the calculation circuit monitoring the A/D-converted value in a lower limit value output period when the A/D-converted value corresponding to a lower limit value of the input range is output from the A/D converter, and performing an offset setting process that sets the offset control value in the offset control register, the offset control value causing the A/D-converted value to become closer to the lower limit target value set in the target register,
the calculation circuit specifying the lower limit value output period based on an indication signal that designates the lower limit value output period and monitoring the A/D-converted value in the lower limit value output period specified by the indication signal.

### Claim 2 (depends on 1)

The analog front-end circuit as defined in claim 1,
the calculation circuit performing a comparison process, a bit determination process, and a decrement process until m becomes 0 from n (n≧m≧0; n and m are integer numbers),
the comparison process setting 1 in bit m−1 of the offset control value set in the offset control register that has an n-bit width and comparing the A/D-converted value with the lower limit target value,
the bit determination process determining a logic level of the bit m−1 of the offset control value to be 1 when the A/D-converted value is smaller than the lower limit target value and determining the logic level of the bit m−1 of the offset control value to be 0 when the A/D-converted value is larger than the lower limit target value, and
the decrement process decrementing m by one.

### Claim 3 (depends on 2)

The analog front-end circuit as defined in claim 2,
the calculation circuit again monitoring the A/D-converted value output from the A/D converter after m has become 0 and the logic levels of all bits of the offset control value set in the offset control register have been determined, and adding 1 to the offset control value set in the offset control register when the A/D-converted value that has been monitored is less than the lower limit target value.

### Claim 4 (depends on 2)

The analog front-end circuit as defined in claim 2,
the calculation circuit including an averaging circuit that averages the A/D-converted values output from the A/D converter, and comparing an average A/D-converted value of a plurality of pixels with the lower limit target value.

### Claim 5 (depends on 1)

The analog front-end circuit as defined in claim 1, further including:
a monitor register, a monitor value of the A/D-converted value output from the A/D converter being set in the monitor register; and
an external interface that allows external access to the target register and the monitor register.

### Claim 6 (depends on 1)

The analog front-end circuit as defined in claim 1,
the lower limit value output period being a black reference pixel output period, the A/D-converted value of a black reference pixel of the image sensor being output in the black reference pixel output period.

### Claim 7 (depends on 6)

The analog front-end circuit as defined in claim 6,
the analog front-end circuit further including a timing generator that generates a plurality of control signals that are supplied to the image sensor,
the timing generator outputting a black reference pixel indication signal that designates the black reference pixel output period as a control signal among the plurality of control signals; and
the calculation circuit monitoring the A/D-converted value output from the A/D converter when the black reference pixel indication signal has become active, and comparing the A/D-converted value with the lower limit target value.

### Claim 8 (depends on 7)

The analog front-end circuit as defined in claim 7,
the timing generator including:
an event information memory; and
a control signal output circuit that generates the plurality of control signals based on information read from the event information memory, and outputs the plurality of control signals that have been generated;
the event information memory storing a pixel number and change event occurrence information at each address, the change event occurrence information specifying a control signal among the plurality of control signals that undergoes a signal level change event at the pixel number; and
the control signal output circuit generating the plurality of control signals based on the pixel number and the change event occurrence information read from the event information memory, and outputting the plurality of control signals that have been generated.

### Claim 9 (depends on 8)

The analog front-end circuit as defined in claim 8,
the pixel number being allocated to bit 0 to bit L of data stored at each address of the event information memory, and the change event occurrence information being allocated to bit L+1 to bit M (L<M; L and M are natural numbers) of the data stored at each address of the event information memory.

### Claim 10 (depends on 9)

The analog front-end circuit as defined in claim 9,
first to (M−L)th control signals among the plurality of control signals being respectively allocated to the bit L+1 to the bit M of the event information memory.

### Claim 11 (depends on 8)

The analog front-end circuit as defined in claim 8,
the control signal output circuit sequentially reading the pixel number and the change event occurrence information in an order from a head address to an end address of the event information memory, and returning a read pointer of the event information memory to the head address before the end address is reached when at least one of the pixel number and the change event occurrence information that have been read is set to finish indication information that indicates that the change event has finished.

### Claim 12 (depends on 1)

The analog front-end circuit as defined in claim 1,
an upper limit target value of the input range of the image signal input from the analog processing circuit to the A/D converter being set in the target register;
the analog processing circuit including a gain control circuit that includes a gain control register and performs gain control on the input image signal to output the image signal based on a gain control value set in the gain control register; and
the calculation circuit monitoring the A/D-converted value in an upper limit value output period when the A/D-converted value corresponding to an upper limit value of the input range is output from the A/D converter, and performing a gain setting process that sets the gain control value in the gain control register, the gain control value causing the A/D-converted value to become closer to the upper limit target value set in the target register.

### Claim 13 (depends on 12)

The analog front-end circuit as defined in claim 12,
the calculation circuit performing the offset setting process using image signals of pixels in Gth to Hth (G<H; G and H are natural numbers) lines of the image sensor, and then performing the gain setting process using image signals of pixels in Ith to Jth (I<J; I and J are natural numbers) lines of the image sensor.

### Claim 14 (depends on 13)

The analog front-end circuit as defined in claim 13,
the calculation circuit repeating a setting process that includes the offset setting process and the gain setting process a plurality of times.

### Claim 15 (depends on 13)

The analog front-end circuit as defined in claim 13,
the calculation circuit performing the offset setting process using the image signals of the pixels in the Gth to Hth lines, omitting the offset setting process and the gain setting process for a line between the Hth line and the Ith line, and then performing the gain setting process using the image signals of the pixels in the Ith to Jth lines.

### Claim 16

An analog front-end circuit comprising:
an analog processing circuit that receives an input image signal from an image sensor, performs a given process on the input image signal, and outputs an image signal;
an A/D converter that A/D-converts the image signal input from the analog processing circuit and outputs an A/D converted value;
a target register, an upper limit target value of an input range of the image signal input from the analog processing circuit to the A/D converter being set in the target register; and
a calculation circuit that monitors the A/D-converted value output from the A/D converter and performs a calculation process,
the analog processing circuit including a gain control circuit that includes a gain control register and performs gain control on the input image signal to output the image signal based on a gain control value set in the gain control register; and
the calculation circuit monitoring the A/D-converted value in an upper limit value output period when the A/D-converted value corresponding to an upper limit value of the input range is output from the A/D converter, and performing a gain setting process that sets the gain control value in the gain control register, the gain control value causing the A/D-converted value to become closer to the upper limit target value set in the target register,
the calculation circuit specifying the upper limit value output period based on an indication signal that designates the upper limit value output period and monitoring the A/D-converted value in the upper limit value output period specified by the indication signal.

### Claim 17 (depends on 16)

The analog front-end circuit as defined in claim 16,
the calculation circuit performing a comparison process, a bit determination process, and a decrement process until i becomes 0 from j (j≧i≧0; i and j are integer numbers,
the comparison process, setting 1 in bit i−1 (j≧i≧0) of the gain control value set in the gain control register that has a j-bit width and comparing the A/D-converted value with the upper limit target value,
the bit determination process determining a logic level of the bit i−1 of the gain control value to be 1 when the A/D-converted value is smaller than the upper limit target value and determining the logic level of the bit i−1 of the gain control value to be 0 when the A/D-converted value is larger than the upper limit target value, and
the decrement process decrementing i by one.

### Claim 18 (depends on 17)

The analog front-end circuit as defined in claim 17,
the calculation circuit again monitoring the A/D-convened value output from the A/D converter after i has become 0 and the logic lewis of all bits of the gain control value set in the gain control register have been determined, and subtracting 1 from the gain control value set in the gain control register when the A/D-converted value that has been monitored is larger than the upper limit target value.

### Claim 19 (depends on 16)

The analog front-end circuit as defined in claim 16,
the upper limit value output period being a white pixel output period, the A/D-converted value of a white pixel of the image sensor being output in the white pixel output period.

### Claim 20 (depends on 1)

An electronic instrument comprising:
the analog front-end circuit as defined in claim 1; and
an image sensor.