# US 7,746,251 B2 · High speed serializer/deserializer transmit architecture

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- Number: US 7,746,251 B2
- Document ID: US7746251B2
- Status: Granted
- Kind: B2
- Application number: 11/939,523
- Filed: 2007-11-13
- Published: 2008-06-12
- Granted: 2010-06-29
- Earliest claimed: 2006-11-13
- Assignees: QUALCOMM Incorporated
- Inventors: Jason Gonzalez
- Web page: https://patentgrep.com/patent/US7746251B2

## CPC

- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.

## Claims

### Claim 1

A serializer circuit comprising:
a pipe input stage that takes eight parallel data bits from a core and latches them using a core byte_clock;
a serializer start block, wherein a tx_ff_ena signal is asserted by the core when the serializer should start, and wherein said tx_ff_ena signal from the core is synchronized to a full-rate clock tx_clk;
a byte-select generator block that generates a byte-select signal that is synchronous to the full-rate clock and maximizes a setup/hold timing margin by loading data after said data has been resting in the pipe input stage for four tx_clk periods;
a serializer output stage that loads the eight parallel data bits from the pipe input stage and then shifts them out serially, and repeats this operation every eight tx_clk periods.