# US 7,746,180 B2 · Phase-locked loop circuit and data reproduction apparatus

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- Number: US 7,746,180 B2
- Document ID: US7746180B2
- Status: Granted
- Kind: B2
- Application number: 12/363,156
- Filed: 2009-01-30
- Published: 2009-06-04
- Granted: 2010-06-29
- Earliest claimed: 2001-07-19
- Assignees: Matsushita Electric Industrial Co., Ltd.
- Inventors: Shinichi Yamane; Seiji Wantanabe
- Web page: https://patentgrep.com/patent/US7746180B2

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/0898: {the source or sink current values being variable (H03L7/0896 takes precedence)}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

## Claims

### Claim 1

A data reproduction apparatus comprising:
a comparator operable to binarize a reproduction signal from a recording medium;
a slice level adjustment circuit operable to adjust a slice level of the comparator;
a phase comparator operable to compare phases of both rising and falling edges of binarized data with a phase of a bit synchronous clock, and operable to output, at least, a comparison result as to both of the rising and falling edges and a comparison result as to only the rising or falling edge;
a switch operable to output the comparison result by switching between outputs of the phase comparator; and
a voltage controlled oscillator operable to generate the bit synchronous clock based on the output of the switch.

### Claim 2 (depends on 1)

The data reproduction apparatus of claim 1, wherein the adjustment for the slice level results from a phase comparison using both edges.

### Claim 3 (depends on 1)

The data reproduction apparatus of claim 1, wherein the adjustment for the phase of the data results from a phase comparison using the rising or falling edge.

### Claim 4 (depends on 1)

The data reproduction apparatus of claim 1, wherein an adjustment for the slice level results from a phase comparison using both edges, and wherein the adjustment for the phase of the data results from a phase comparison of the rising or falling edge.

### Claim 5 (depends on 1)

The data reproduction apparatus of claim 1, wherein the recording medium is an optical disk.