# US 7,746,178 B1 · Digital offset phase-locked loop

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- Number: US 7,746,178 B1
- Document ID: US7746178B1
- Status: Granted
- Kind: B1
- Application number: 12/341,528
- Filed: 2008-12-22
- Granted: 2010-06-29
- Earliest claimed: 2007-12-21
- Assignees: RF Micro Devices, Inc.
- Inventors: Scott Robert Humphreys; Stephen T. Janesch
- Web page: https://patentgrep.com/patent/US7746178B1

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)}
- H03L 7/16: Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L 2207/12: Indirect frequency synthesis using a mixer in the phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

The present invention relates to a digital offset phase-locked loop (DOPLL), which may have advantages of size, simplicity, performance, design portability, or any combination thereof, compared to analog-based phase-locked loops (PLLs). The DOPLL may include a digital controlled oscillator (DCO), which provides a controllable frequency output signal based on a digital control signal, a radio frequency (RF) mixer circuit, which provides a reduced-frequency feedback signal based on the controllable frequency output signal without reducing loop gain, a time-to-digital converter (TDC), which provides a digital feedback signal that is a time representation of the reduced-frequency feedback signal, and digital PLL circuitry, which provides the digital control signal based on the digital feedback signal and a digital setpoint signal.

## Claims

### Claim 1

A radio frequency (RF) circuit comprising:
a first digital controlled oscillator (DCO) adapted to:
receive a first digital control signal; and
provide an RF output signal having a first frequency and a first phase, such that the first frequency is based on the first digital control signal;
a first RF mixer circuit adapted to:
receive a first local oscillator (LO) signal and the RF output signal; and
provide a first intermediate frequency (IF) signal based on mixing the first LO signal and the RF output signal;
a time-to-digital converter adapted to:
receive and convert the first IF signal into a digital time representation of the first IF signal; and
provide a first digital signal based on the digital time representation, such that the first digital signal is indicative of the first phase and the first frequency; and
digital loop circuitry adapted to:
receive a digital setpoint signal;
receive the first digital signal; and
provide the first digital control signal based on a difference between the digital setpoint signal and the first digital signal,
wherein the first frequency is controlled to be about equal to a desired frequency represented by the digital setpoint signal.

### Claim 2 (depends on 1)

The RF circuit of claim 1 wherein:
the first LO signal has a first LO frequency and a first LO phase;
the first IF signal has a first IF frequency and a first IF phase;
the first IF frequency is based on a difference between the first LO frequency and the first frequency;
the first IF phase is based on the first LO phase and the first phase; and
the first digital signal is further based on the first IF phase.

### Claim 3 (depends on 2)

The RF circuit of claim 2 wherein the first RF mixer circuit comprises:
an RF mixer adapted to:
receive the first LO signal and the RF output signal; and
mix the first LO signal and the RF output signal to provide a second IF signal, which has an upper sideband component and a lower sideband component; and
a sideband selection filter adapted to:
receive the second IF signal; and
filter the second IF signal to remove the upper sideband component and provide the first IF signal.

### Claim 4 (depends on 2)

The RF circuit of claim 2 wherein the first IF frequency is chosen to be about equal to the first frequency divided by an integer.

### Claim 5 (depends on 2)

The RF circuit of claim 2 wherein the first IF frequency is chosen, such that there is at least a minimum offset between one or more frequencies of spurs appearing in the first LO signal and the first LO frequency.

### Claim 6 (depends on 1)

The RF circuit of claim 1 wherein:
the digital loop circuitry comprises:
control circuitry adapted to select between a coarse tuning mode and a fine tuning mode;
a digital phase-locked loop (PLL) circuit, which during the fine tuning mode is adapted to:
receive the digital setpoint signal, which has a first reference phase;
receive the first digital signal;
provide a first digital phase error signal based on a first phase difference between the first reference phase and the first phase; and
filter the first digital phase error signal to provide the first digital control signal; and
a digital frequency-locked loop (FLL) circuit, which during the coarse tuning mode is adapted to:
receive the digital setpoint signal, which has a first reference frequency;
receive the first digital signal;
provide a first digital frequency error signal based on a difference associated with the first reference frequency and the first frequency; and
filter the first digital frequency error signal to provide a second digital control signal; and
the first DCO is further adapted to receive the second digital control signal, and the first frequency is further based on the second digital control signal.

### Claim 7 (depends on 6)

The RF circuit of claim 6 wherein the first DCO comprises:
a switched capacitor bank having a plurality of capacitors and adapted to:
receive the second digital control signal; and
select at least one of the plurality of capacitors based on the second digital control signal;
a digital-to-analog converter (DAC) adapted to:
receive the first digital control signal; and
provide an analog control signal based on the first digital control signal; and
a voltage controlled oscillator (VCO) adapted to:
receive the analog control signal; and
provide the RF output signal based on the analog control signal and the selection of the at least one of the plurality of capacitors.

### Claim 8 (depends on 1)

The RF circuit of claim 1 wherein the digital loop circuitry comprises a digital phase-locked loop (PLL) circuit adapted to:
receive the digital setpoint signal, which has a first reference phase;
receive the first digital signal;
provide a first digital phase error signal based on a first phase difference between the first reference phase and the first phase; and
filter the first digital phase error signal to provide the first digital control signal.

### Claim 9 (depends on 8)

The RF circuit of claim 8 wherein the first DCO comprises a switched capacitor bank having a plurality of capacitors and adapted to:
receive the first digital control signal; and
select at least one of the plurality of capacitors based on the first digital control signal,
wherein the RF output signal is based on the selection of the at least one of the plurality of capacitors.

### Claim 10 (depends on 8)

The RF circuit of claim 8 wherein the first DCO comprises:
a digital-to-analog converter (DAC) adapted to:
receive the first digital control signal; and
provide an analog control signal based on the first digital control signal; and
a voltage controlled oscillator (VCO) adapted to:
receive the analog control signal; and
provide the RF output signal based on the analog control signal.

### Claim 11 (depends on 8)

The RF circuit of claim 8 wherein:
the digital PLL circuit is further adapted to filter the first digital phase error signal to further provide a second digital control signal, such that the second digital control signal has bits of a higher significance than the first digital control signal; and
the first DCO is further adapted to receive the second digital control signal, and the first frequency is further based on the second digital control signal.

### Claim 12 (depends on 11)

The RF circuit of claim 11 wherein the first DCO comprises:
a switched capacitor bank having a plurality of capacitors and adapted to:
receive the second digital control signal; and
select at least one of the plurality of capacitors based on the second digital control signal;
a digital-to-analog converter (DAC) adapted to:
receive the first digital control signal; and
provide an analog control signal based on the first digital control signal; and
a voltage controlled oscillator (VCO) adapted to:
receive the analog control signal; and
provide the RF output signal based on the analog control signal and the selection of the at least one of the plurality of capacitors.

### Claim 13 (depends on 8)

The RF circuit of claim 8 wherein the time-to-digital converter is further adapted to:
receive a first reference signal; and
convert the first IF signal into the first digital signal using the first reference signal,
wherein the first IF signal is continuous time valued and the first digital signal is discrete time valued.

### Claim 14 (depends on 13)

The RF circuit of claim 13 wherein the first reference signal is sampled using the first IF signal as a sampling clock.

### Claim 15 (depends on 13)

The RF circuit of claim 13 further comprising an LO adapted to:
receive the first reference signal; and
provide the first LO signal based on the first reference signal.

### Claim 16 (depends on 8)

The RF circuit of claim 8 further comprising an LO adapted to:
receive a first reference signal; and
provide the first LO signal based on the first reference signal.

### Claim 17 (depends on 16)

The RF circuit of claim 16 wherein the RF circuit is a dual loop PLL, such that the first DCO, the first RF mixer circuit, the time-to-digital converter, and the digital loop circuitry form a first PLL loop, and the LO provides a second PLL loop.

### Claim 18 (depends on 16)

The RF circuit of claim 16 wherein the first LO signal has an LO frequency, which is chosen to avoid an RF spur on the RF output signal.

### Claim 19 (depends on 8)

The RF circuit of claim 8 wherein:
the first DCO, the first RF mixer circuit, the time-to-digital converter, and the digital loop circuitry form a PLL loop having a PLL loop bandwidth;
the digital setpoint signal is modulated to frequency modulate the RF output signal; and
the RF output signal has a modulation bandwidth.

### Claim 20 (depends on 19)

The RF circuit of claim 19 wherein the modulation bandwidth is about less than the PLL loop bandwidth.

### Claim 21 (depends on 8)

The RF circuit of claim 8 wherein:
the first DCO, the first RF mixer circuit, the time-to-digital converter, and the digital loop circuitry forms a PLL loop having a PLL loop bandwidth;
the digital setpoint signal is modulated to phase modulate the RF output signal; and
the RF output signal has a modulation bandwidth, which is about less than the PLL loop bandwidth.

### Claim 22 (depends on 8)

The RF circuit of claim 8 wherein the digital PLL circuit comprises:
a digital phase detector adapted to:
receive the digital setpoint signal;
receive the first digital signal; and
provide the first digital phase error signal based on the first phase difference between the first reference phase and the first phase; and
a digital loop filter adapted to:
receive the first digital phase error signal; and
filter the first digital phase error signal to provide the first digital control signal.

### Claim 23 (depends on 22)

The RF circuit of claim 22 wherein:
the digital phase detector is further adapted to:
receive the first IF signal;
sample the digital setpoint signal using the first IF signal as a sampling clock;
sample the first digital signal using the first IF signal as a sampling clock; and
provide the first digital phase error signal based on the sampled digital setpoint signal and the sampled first digital signal; and
the digital loop filter is further adapted to:
receive the first IF signal;
sample the first digital phase error signal using the first IF signal as a sampling clock; and
filter the sampled first digital phase error signal to provide the first digital control signal.

### Claim 24 (depends on 22)

The RF circuit of claim 22 wherein:
the digital phase detector is further adapted to:
receive a first reference signal;
sample the digital setpoint signal using the first reference signal as a sampling clock;
sample the first digital signal using the first reference signal as a sampling clock; and
provide the first digital phase error signal based on the sampled digital setpoint signal and the sampled first digital signal; and
the digital loop filter is further adapted to:
receive the first reference signal;
sample the first digital phase error signal using the first reference signal as a sampling clock; and
filter the sampled first digital phase error signal to provide the first digital control signal.

### Claim 25 (depends on 8)

The RF circuit of claim 8 wherein the digital PLL circuit comprises:
a synchronizer adapted to:
receive the first IF signal;
receive the digital setpoint signal; and
synchronize the digital setpoint signal using the first IF signal as a sampling clock to provide a synchronized digital setpoint signal;
a phase accumulator adapted to:
receive the first IF signal;
receive the synchronized digital setpoint signal;
sample the synchronized digital setpoint signal using the first IF signal as a sampling clock;
accumulate phase of the sampled synchronized digital setpoint signal; and
provide an accumulated phase signal based on the accumulated phase of the sampled synchronized digital setpoint signal;
a digital phase detector adapted to:
receive the first IF signal;
receive the accumulated phase signal;
sample the accumulated phase signal using the first IF signal as a sampling clock;
receive the first digital signal;
sample the first digital signal using the first IF signal as a sampling clock; and
provide the first digital phase error signal based on the sampled accumulated phase signal and the sampled first digital signal; and
a digital loop filter adapted to:
receive the first IF signal;
sample the first digital phase error signal using the first IF signal as a sampling clock; and
filter the sampled first digital phase error signal to provide the first digital control signal.

### Claim 26 (depends on 8)

The RF circuit of claim 8 wherein the digital PLL circuit comprises:
a digital phase detector adapted to:
receive the first IF signal;
receive the digital setpoint signal;
sample the digital setpoint signal using the first IF signal as a sampling clock;
receive the first digital signal;
sample the first digital signal using the first IF signal as a sampling clock; and
provide the first digital phase error signal based on the sampled digital setpoint signal and the sampled first digital signal;
a digital loop filter adapted to:
receive the first IF signal;
sample the first digital phase error signal using the first IF signal as a sampling clock; and
filter the sampled first digital phase error signal to provide a loop filter output signal; and
a delta-sigma modulator adapted to:
receive the first IF signal;
receive the loop filter output signal;
sample the loop filter output signal using the first IF signal as a sampling clock; and
modulate the sampled loop filter output signal to provide the first digital control signal.

### Claim 27 (depends on 8)

The RF circuit of claim 8 wherein the digital PLL circuit comprises:
a synchronizer adapted to:
receive the first IF signal;
receive the digital setpoint signal; and
synchronize the digital setpoint signal using the first IF signal as a sampling clock to provide a synchronized digital setpoint signal;
a phase accumulator adapted to:
receive the first IF signal;
receive the synchronized digital setpoint signal;
sample the synchronized digital setpoint signal using the first IF signal as a sampling clock;
accumulate phase of the sampled synchronized digital setpoint signal; and
provide an accumulated phase signal based on the accumulated phase of the sampled synchronized digital setpoint signal;
a digital phase detector adapted to:
receive the first IF signal;
receive the accumulated phase signal;
sample the accumulated phase signal using the first IF signal as a sampling clock;
receive the first digital signal;
sample the first digital signal using the first IF signal as a sampling clock; and
provide the first digital phase error signal based on the sampled accumulated phase signal and the sampled first digital signal;
a digital loop filter adapted to:
receive the first IF signal;
sample the first digital phase error signal using the first IF signal as a sampling clock; and
filter the sampled first digital phase error signal to provide a loop filter output signal; and
a delta-sigma modulator adapted to:
receive the first IF signal;
receive the loop filter output signal;
sample the loop filter output signal using the first IF signal as a sampling clock; and
modulate the sampled loop filter output signal to provide the first digital control signal.

### Claim 28 (depends on 1)

The RF circuit of claim 1 wherein the digital loop circuitry comprises:
control circuitry adapted to select a coarse tuning mode; and
a digital frequency-locked loop (FLL) circuit, which during the coarse tuning mode is adapted to:
receive the digital setpoint signal, which has a first reference frequency;
receive the first digital signal;
provide a first digital frequency error signal based on a difference associated with the first reference frequency and the first frequency; and
filter the first digital frequency error signal to provide the first digital control signal.

### Claim 29

A method comprising:
providing a first digital controlled oscillator (DCO), a first radio frequency (RF) mixer circuit, and a time-to-digital converter;
receiving a first digital control signal;
providing an RF output signal having a first frequency and a first phase, such that the first frequency is based on the first digital control signal;
receiving a first local oscillator (LO) signal and the RF output signal;
mixing the first LO signal and the RF output signal to provide a first intermediate frequency (IF) signal;
receiving and converting the first IF signal into a digital time representation of the first IF signal;
providing a first digital signal based on the digital time representation, such that the first digital signal is indicative of the first phase and the first frequency;
receiving a digital setpoint signal; and
providing the first digital control signal based on a difference between the digital setpoint signal and the first digital signal,
wherein the first frequency is controlled to be about equal to a desired frequency represented by the digital setpoint signal.