# US 7,746,176 B2 · Receiver comprising an amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,176 B2 - Document ID: US7746176B2 - Status: Granted - Kind: B2 - Application number: 11/815,966 - Filed: 2006-01-30 - Published: 2008-12-04 - Granted: 2010-06-29 - Earliest claimed: 2005-02-09 - Assignees: ST-Ericsson SA - Inventors: Edwin Van Der Heijden; Hugo Veenstra - Web page: https://patentgrep.com/patent/US7746176B2 ## CPC - H03F 3/45089: {Non-folded cascode stages} - H03F 2200/372: Noise reduction and elimination in amplifier - H03F 2203/45316: the AAC comprising one or more discrete inductive elements or coils - H03F 2203/45386: the AAC comprising one or more coils in the source circuit - H03F: AMPLIFIERS ## Abstract The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a, 12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising a circuit (54) for compensating a series input impedance of the amplifier (31-34). ## Claims ### Claim 1 A receiver comprising an amplifier configured to amplify an antenna signal, which amplifier comprises an amplifier input and an amplifier output, the amplifier input being a single ended input configured to receive the antenna signal, the amplifier output being a differential output, and the amplifier comprising a circuit configured to compensate a series input impedance of the amplifier. ### Claim 2 (depends on 1) A receiver according to claim 1, the amplifier comprising a first transistor and a second transistor, control electrodes of both transistors being coupled to each other via a first element, first main electrodes of both transistors being coupled to each other via a second element, and the circuit configured to compensate being coupled to the first element. ### Claim 3 (depends on 2) A receiver according to claim 2, the circuit comprising a third transistor, a control electrode of the third transistor being coupled to a control electrode of the second transistor, a first main electrode of the third transistor being coupled to ground via a parallel circuit of a current source and a capacitor, a second main electrode of the third transistor being coupled to a voltage supply. ### Claim 4 (depends on 2) A receiver according to claim 2, second main electrodes of both transistors being coupled to a cascode circuit comprising the amplifier output. ### Claim 5 (depends on 2) A receiver according to claim 2, the first element comprising a differential inductor with a center tap. ### Claim 6 (depends on 5) A receiver according to claim 5, the center tap being coupled to a voltage source. ### Claim 7 (depends on 2) A receiver according to claim 2, a control electrode of the first transistor being coupled via a further capacitor to the amplifier input. ### Claim 8 An amplifier configured to amplify an antenna signal in a receiver, which amplifier comprises an amplifier input and an amplifier output, the amplifier input being a single ended input configured to receive the antenna signal, the amplifier output being a differential output, and the amplifier comprising a means for compensating a series input impedance of the amplifier. ### Claim 9 A method of amplifying an antenna signal in a receiver, the method comprising: receiving an antenna signal at a single-ended input of an amplifier; compensating a series input impedance of the amplifier during amplification of the antenna signal; and outputting the amplified antenna signal at a differential output of the amplifier. ### Claim 10 (depends on 9) A method in accordance with claim 9 wherein compensating a series input impedance of the amplifier comprises providing a negative input resistance. ### Claim 11 (depends on 9) A method in accordance with claim 9 wherein compensating a series input impedance of the amplifier occurs in an absence of a noise generating resistor. ### Claim 12 (depends on 9) A method in accordance with claim 9 wherein compensating a series input impedance of the amplifier obtains an input power match. ### Claim 13 (depends on 9) A method in accordance with claim 9 wherein the amplifier comprises a first transistor and a second transistor, a first element coupling control electrodes of the first and second transistors to each other, and a second element coupling first main electrodes of the first and second transistors to each other, and wherein a circuit configured to compensate a series input impedance of the amplifier is coupled to the first element. ### Claim 14 (depends on 13) A method in accordance with claim 13 wherein the circuit comprises a third transistor, the third transistor comprising: a control electrode coupled to a control electrode of the second transistor, a first main electrode coupled to ground via a parallel circuit of a current source and a first capacitor, and a second main electrode coupled to a voltage supply. ### Claim 15 (depends on 13) A method in accordance with claim 13 wherein second main electrodes of the first and second transistors are coupled to a cascode circuit comprising the differential output of the amplifier. ### Claim 16 (depends on 13) A method in accordance with claim 13 wherein the first element comprises a differential inductor with a center tap. ### Claim 17 (depends on 16) A method in accordance with claim 16 wherein the center tap is coupled to a voltage source. ### Claim 18 (depends on 13) A method in accordance with claim 13 wherein the first element comprises two serial inductors. ### Claim 19 (depends on 18) A method in accordance with claim 18 wherein the common point of the two serial inductors is coupled to a voltage source. ### Claim 20 (depends on 13) A method in accordance with claim 13 wherein a control electrode of the first transistor is coupled to the single-ended amplifier input via a second capacitor.