# US 7,746,168 B2 · Bias circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,168 B2 - Document ID: US7746168B2 - Status: Granted - Kind: B2 - Application number: 11/505,442 - Filed: 2006-08-17 - Published: 2007-07-05 - Granted: 2010-06-29 - Earliest claimed: 2006-01-04 - Assignees: Fujitsu Semiconductor Limited - Inventors: Kazuaki Oishi - Web page: https://patentgrep.com/patent/US7746168B2 ## CPC - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H03F 3/45188: {Non-folded cascode stages} - H03F 2203/45244: the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors - H03F 2203/45454: the CSC comprising biasing means controlled by the input signal - H03F 2203/45466: the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit - H03F 2203/45508: the CSC comprising a voltage generating circuit as bias circuit for the CSC - H03F: AMPLIFIERS ## Abstract A bias circuit of a resistance load differential amplifier comprises a first differential pair and a control unit for controlling a tail current of the first differential pair, and making an output current of the first differential pair being in inverse proportion to a load resistance in the resistance load differential amplifier when applying a constant potential difference to an input of the first differential pair. The control unit further controls a tail current of a second differential pair constituting the resistance load differential amplifier, and makes the tail current of the second differential pair being in direct proportion to the tail current of the first differential pair. ## Claims ### Claim 1 A bias circuit of a resistance load differential amplifier, comprising: a first differential pair; and a control unit for controlling a tail current of the first differential pair, and making an output current of the first differential pair being in inverse proportion to a load resistance in the resistance load differential amplifier when applying a constant potential difference to an input of the first differential pair, wherein: the control unit further controls a tail current of a second differential pair constituting the resistance load differential amplifier, and makes the tail current of the second differential pair being in direct proportion to the tail current of the first differential pair. ### Claim 2 (depends on 1) The bias circuit according to claim 1, wherein: the first differential pair and the second differential pair employ the same circuit configuration. ### Claim 3 (depends on 2) The bias circuit according to claim 2, wherein: transistors constituting the first differential pair and transistors constituting the second differential pair have the same transistor size ratio. ### Claim 4 (depends on 1) The bias circuit according to claim 1, wherein: the control unit comprises: a current mirror for causing currents in the same quantity to flow into respective transistors in a pair that constitutes the first differential pair; a current source for causing the current in inverse proportion to a load resistance to flow; and a tail current control unit for controlling a tail current of the first differential pair, and making the output current correspond to the current caused to flow by the current source. ### Claim 5 (depends on 4) The bias circuit according to claim 4, wherein: the tail current control unit controls the tail current of the first differential pair such that a voltage generated at an output node of the first differential pair when the current source causes the current to flow into the output node of the first differential pair is a prescribed reference voltage. ### Claim 6 (depends on 5) The bias circuit according to claim 5, wherein: the tail current control unit comprises a differential amplifier for comparing the voltage generated at the output node of the first differential pair and input to the differential amplifier with the prescribed reference voltage, and controls a transistor determining the tail current of the first differential pair by the output of the differential amplifier. ### Claim 7 (depends on 6) The bias circuit according to claim 6, wherein: a capacitor or a capacitor and resistor in a series connection is connected between an input and an output of the differential amplifier. ### Claim 8 (depends on 6) The bias circuit according to claim 6, wherein: the control unit controls a transistor that determines the tail current of the second differential pair by the output of the differential amplifier. ### Claim 9 (depends on 5) The bias circuit according to claim 5, wherein: the tail current control unit comprises: a differential amplifier for comparing the voltage generated at the output node of the first differential pair and input to the differential amplifier with the prescribed reference voltage; first and second transistors for controlling a current based on an output of the differential amplifier; and a third transistor constituting a current mirror together with the transistor that determines the tail current of the first differential pair, and being a diode-connected transistor, wherein: the current controlled by the first transistor is caused to flow into the third transistor; and the control unit controls the transistor that determines the tail current of the second differential pair by the current controlled by the second transistor. ### Claim 10 (depends on 9) The bias circuit according to claim 9, wherein: the control unit further comprises a fourth transistor constituting a current mirror together with the transistor that determines the tail current of the second differential pair, and being a diode-connected transistor; and the current controlled by the second transistor is caused to flow into the fourth transistor. ### Claim 11 (depends on 9) The bias circuit according to claim 9, wherein: a capacitor or a capacitor and resistor in a series connection is connected between an input of the differential amplifier and a connection node between the third transistor and the transistor that determines the tail current of the first differential pair.