# US 7,746,166 B2 · Integrated circuit including filter circuit arrangement

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- Number: US 7,746,166 B2
- Document ID: US7746166B2
- Status: Granted
- Kind: B2
- Application number: 11/948,391
- Filed: 2007-11-30
- Published: 2009-07-02
- Granted: 2010-06-29
- Earliest claimed: 2007-11-30
- Assignees: Infineon Technologies AG
- Inventors: Stefan Hermann Groiss; Elmar Bach
- Web page: https://patentgrep.com/patent/US7746166B2

## CPC

- H03H 11/1291: {Current or voltage controlled filters}
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

An integrated circuit includes a filter circuit that has at least one active device, wherein the active device has adjustable transconductance.

## Claims

### Claim 1

A filter circuit arrangement comprising:
a first pair of transistors;
a first and a second switch for switching between a first and a second frequency band operating mode;
a first connection of the first switch being connected to a control gate of the first transistor of the first pair of transistors;
a second connection of the first switch being connected to a control gate of the second transistor of the first pair of transistors;
a first connection of the second switch being connected to the control gate of the first transistor of the first pair of transistors;
a second connection of the second switch being connected to a reference voltage;
a second pair of transistors;
a third switch;
a first connection of the third switch being connected to the first transistor of first pair of transistors and to the first transistor of the second pair of transistors; and
a second connection of the third switch being connected to the second transistor of the first pair of transistors and to the second transistor of the second pair of transistors.

### Claim 2 (depends on 1)

The filter circuit arrangement of claim 1, further comprising a third pair of transistors, and a fourth and a fifth switch, a first connection of the fourth switch being connected to a control gate of the first transistor of the third pair of transistors, a second connection of the fourth switch being connected to a control gate of the second transistor of the third pair of transistors, a first connection of the fifth switch being connected to the control gate of the first transistor of the third pair of transistors, and a second connection of the fifth switch being connected to a reference voltage.

### Claim 3

A filter circuit arrangement comprising:
a first set of transistors;
a first and a second and a third and a fourth switch for switching between a first and a second and a third frequency band operating mode;
a first connection of the first switch being connected to a control gate of a first transistor of the first set of transistors;
a second connection of the first switch being connected to a control gate of a second transistor of the first set of transistors;
a first connection of the second switch being connected to the control gate of the first transistor of the first set of transistors;
a second connection of the second switch being connected to a reference voltage;
a first connection of the third switch being connected to a control gate of a third transistor of the first set of transistors;
a second connection of the third switch being connected to the control gate of the second transistor of the first set of transistors;
a first connection of the fourth switch being connected to the control gate of the third transistor of the first set of transistors;
a second connection of the fourth switch being connected to a reference voltage
second set of transistors;
a fifth and a sixth switch;
a first connection of the fifth switch being connected to the first transistor of the first set of transistors and to a first transistor of the second set of transistors;
a second connection of the fifth switch being connected to the second transistor of the first set of transistors and to a second transistor of the second set of transistors;
a first connection of the sixth switch being connected to the third transistor of the first set of transistors and to a third transistor of the second set of transistors; and
a second connection of the sixth switch being connected to the second transistor of the first set of transistors and to the second transistor of the second set of transistors.