# US 7,746,162 B2 · Apparatus and method for waking up a circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,162 B2 - Document ID: US7746162B2 - Status: Granted - Kind: B2 - Application number: 12/022,407 - Filed: 2008-01-30 - Published: 2009-07-30 - Granted: 2010-06-29 - Earliest claimed: 2008-01-30 - Assignees: Infineon Technologies AG - Inventors: Vincent Gouin - Web page: https://patentgrep.com/patent/US7746162B2 ## CPC - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current. ## Claims ### Claim 1 A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage, wherein the circuit comprises a memory circuit, and wherein the constant wake-up current is less than or equal to an access current of the memory circuit. ### Claim 2 (depends on 1) The method of claim 1, wherein charging comprises determining the constant wake-up current based on a reference current. ### Claim 3 (depends on 1) The method of claim 1, further comprising adapting the wake-up current to the access current depending on at least one of a process variation, a temperature variation, and a supply voltage variation. ### Claim 4 An apparatus, comprising: a circuit portion; a switch configured to selectively couple a supply voltage input of the circuit portion to a supply voltage; a current source configured to generate a first current that is smaller than or equal to a current flowing through the supply voltage input of the circuit portion during a normal operation of the circuit portion; and a control circuit configured to control a state of the switch depending on the first current, wherein the control circuit comprises an operational amplifier, an output of the operational amplifier being coupled with a control terminal of the switch. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the apparatus is configured such that when the switch is coupling the supply voltage input of the circuit portion to the supply voltage, a current flowing through the supply voltage input of the circuit portion is maintained at a constant value for a predetermined time period. ### Claim 6 (depends on 4) The apparatus of claim 4, wherein the switch comprises a transistor. ### Claim 7 (depends on 4) The apparatus of claim 4, wherein the control circuit comprises at least a portion of a current mirror circuit. ### Claim 8 (depends on 4) The apparatus of claim 4, wherein the current source comprises a transistor configured to be operated in a linear regime. ### Claim 9 An apparatus, comprising: a memory; a first switch comprising a control terminal, a first terminal, and a second terminal, the first terminal configured to be coupled with a supply voltage and the second terminal coupled with an input of the memory; an amplifier comprising an output coupled with the control terminal of the first switch, a first input coupled with the first terminal of the first switch, and a second input; and a current source coupled with the second input of the amplifier. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the first input of the amplifier is a negative input and the second input of the amplifier is a positive input. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the first terminal of the first switch is coupled to a first circuit element, wherein the current source is coupled to a second circuit element, and wherein the second circuit element is configured to be coupled to the supply voltage. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the first circuit element and the second element are each selected from a group comprising a resistor and a transistor. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the amplifier comprises a differential pair of transistors. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the amplifier comprises an inverter. ### Claim 15 (depends on 9) The apparatus of claim 9, wherein the current source comprises a transistor configured to operate in linear regime. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the current source comprises an n-type metal-oxide semiconductor (NMOS) transistor configured to be operated in linear regime and a p-type metal-oxide semiconductor (PMOS) transistor configured to be operated in linear regime, and the current source is configured to output a current dependent on both a current flowing through the NMOS transistor and a current through the PMOS transistor. ### Claim 17 (depends on 9) The apparatus of claim 9, further comprising a second switch configured to selectively control the electronic circuit between a sleep mode and an active mode. ### Claim 18 An apparatus, comprising: a circuit portion; a switch configured to selectively couple a supply voltage input of the circuit portion to a supply voltage; a current source configured to generate a first current that is smaller than or equal to a current flowing through the supply voltage input of the circuit portion during a normal operation of the circuit portion; and a control circuit configured to control a state of the switch depending on the first current, wherein the circuit portion comprises a memory circuit, and wherein the current flowing through the supply voltage input of the circuit portion during the normal operation is an access current of the memory circuit. ### Claim 19 An apparatus, comprising: a circuit portion; a first switch having a control input and configured to selectively couple an input of the circuit portion to a supply voltage; a current source configured to generate a first current; a control circuit configured to control a state of a first switch so as to depend on the first current; and a second switch configured to selectively couple the control input of the first switch with the supply voltage, wherein the control circuit comprises an operational amplifier, an output of the operational amplifier being coupled with the control input of the first switch. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the apparatus is configured such that when the first switch is coupling the input of the circuit portion to the supply voltage, a current flowing through the input of the circuit portion is maintained at a constant value for a predetermined time period. ### Claim 21 (depends on 19) The apparatus of claim 19, wherein the first switch comprises a transistor. ### Claim 22 (depends on 19) The apparatus of claim 19, wherein the control circuit comprises at least a portion of a current mirror circuit.