# US 7,746,157 B2 · Electric circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,157 B2 - Document ID: US7746157B2 - Status: Granted - Kind: B2 - Application number: 12/041,042 - Filed: 2008-03-03 - Published: 2008-07-17 - Granted: 2010-06-29 - Earliest claimed: 2001-11-28 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Hajime Kimura; Yasuko Watanabe - Web page: https://patentgrep.com/patent/US7746157B2 ## CPC - G09G 3/3225: using an active matrix - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - H03F 3/45076: {characterised by the way of implementation of the active amplifying circuit in the differential amplifier} - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03K 19/00384: {in field effect transistor circuits} - H03K 19/01728: {in synchronous circuits, i.e. by using clock signals} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - G09G 2300/0833: forming a linear amplifier or follower - G09G 2300/0876: Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes - H03F 3/45: Differential amplifiers (differential sense amplifiers G11C7/062) - H03F 2203/45112: the biasing of the differential amplifier being controlled from the input or the output signal - H03F 2203/45628: the LC comprising bias stabilisation means, e.g. DC level stabilisation means, and temperature coefficient dependent control, e.g. DC level shifting means - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor. ## Claims ### Claim 1 A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a capacitor, wherein: one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the first wiring is kept at a first potential, the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the second transistor is electrically connected to the first wiring, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, one of a source and a drain of the fifth transistor is electrically connected to a second wiring, wherein the second wiring is kept at a second potential, a first electrode of the capacitor is electrically connected to the gate of the first transistor, and a second electrode of the capacitor is electrically connected to the other of the source and the drain of the fourth transistor. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the other of the source and the drain of the first transistor is electrically connected to a pixel. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the other of the source and the drain of the first transistor is electrically connected to a pixel, and wherein the pixel includes one of a liquid crystal element and a light-emitting element. ### Claim 4 A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; and a capacitor, wherein: one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the first wiring is kept at a first potential, the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the second transistor is electrically connected to the first wiring, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, one of a source and a drain of the fifth transistor is electrically connected to a second wiring, wherein the second wiring is kept at a second potential, a first electrode of the capacitor is electrically connected to the gate of the first transistor, a second electrode of the capacitor is electrically connected to the other of the source and the drain of the fourth transistor, and a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the other of the source and the drain of the first transistor is electrically connected to a pixel. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the other of the source and the drain of the first transistor is electrically connected to a pixel, and wherein the pixel includes one of a liquid crystal element and a light-emitting element. ### Claim 7 (depends on 4) The semiconductor device according to claim 4, wherein the other of the source and the drain of the sixth transistor is electrically connected to a pixel. ### Claim 8 (depends on 4) The semiconductor device according to claim 4, wherein the other of the source and the drain of the sixth transistor is electrically connected to a pixel, and wherein the pixel includes one of a liquid crystal element and a light-emitting element. ### Claim 9 The semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; and a capacitor, wherein: one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the first wiring is kept at a first potential, the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the second transistor is electrically connected to the first wiring, one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, one of a source and a drain of the fifth transistor is electrically connected to a second wiring, wherein the second wiring is kept at a second potential, a first electrode of the capacitor is electrically connected to the gate of the first transistor, a second electrode of the capacitor is electrically connected to the other of the source and the drain of the fourth transistor, a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor, a conduction type of the first transistor is a p-channel type, and the first potential of the first wiring is lower than the second potential of the second wiring. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the other of the source and the drain of the first transistor is electrically connected to a pixel. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein the other of the source and the drain of the first transistor is electrically connected to a pixel, and wherein the pixel includes one of a liquid crystal element and a light-emitting element. ### Claim 12 (depends on 9) The semiconductor device according to claim 9, wherein the other of the source and the drain of the sixth transistor is electrically connected to a pixel. ### Claim 13 (depends on 9) The semiconductor device according to claim 9, wherein the other of the source and the drain of the sixth transistor is electrically connected to a pixel, and wherein the pixel includes one of a liquid crystal element and a light-emitting element.