# US 7,746,152 B2 · Switch circuit device, and wireless circuit device and sampling circuit device employing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,152 B2 - Document ID: US7746152B2 - Status: Granted - Kind: B2 - Application number: 11/806,972 - Filed: 2007-06-05 - Published: 2007-12-13 - Granted: 2010-06-29 - Earliest claimed: 2006-06-07 - Assignees: Panasonic Corporation - Inventors: Toshifumi Nakatani; Mikihiro Shimada - Web page: https://patentgrep.com/patent/US7746152B2 ## CPC - H03K 17/063: {in field-effect transistor switches} - G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence) - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H03K 2017/066: {Maximizing the OFF-resistance instead of minimizing the ON-resistance} - H03K 2217/0018: Special modifications or use of the back gate voltage of a FET - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A switch circuit device with improved insertion loss characteristics and isolation characteristics is provided. The switch circuit of the present invention includes a plurality of n-ch MOSFETs whose gates are connected together and whose drains and sources are connected in series, a p-ch MOSFET whose gate is connected to the gates of the plurality of n-ch MOSFETs and whose drain is connected to the source and drain of at least one pair of adjacent n-ch MOSFETs, and a voltage changing circuit for applying a low voltage to the source of the p-ch MOSFET while a high-level control voltage is applied to the gate of the p-ch MOSFET, and a high voltage to the source of the p-ch MOSFET while a low-level control voltage is applied to the gate of the p-ch MOSFET. ## Claims ### Claim 1 A switch circuit device comprising: a plurality of n-ch MOSFETs whose gates are connected together and whose drains and sources are connected in series; a p-ch MOSFET whose gate is connected to the gates of the plurality of n-ch MOSFETs and whose drain is connected to the source and drain connected to each other of at least one pair of adjacent n-ch MOSFETs of the plurality of n-ch MOSFETs; and a voltage changing circuit for applying a low voltage to the source of the p-ch MOSFET while a high-level control voltage is applied to the gate of the p-ch MOSFET, the low voltage being lower than the high-level control voltage, and a high voltage to the source of the p-ch MOSFET while a low-level control voltage is applied to the gate of the p-ch MOSFET, the high voltage being higher than the low-level control voltage. ### Claim 2 (depends on 1) The switch circuit device according to claim 1, wherein the voltage changing circuit includes an odd number of inverters connected in series for inverting and outputting a control voltage to be applied to the gate of the p-ch MOSFET. ### Claim 3 (depends on 1) The switch circuit device according to claim 1, wherein the high voltage applied to the source of the p-ch MOSFET is equal to a voltage applied to a back gate of the p-ch MOSFET. ### Claim 4 (depends on 1) The switch circuit device according to claim 1, wherein the high voltage applied to the source of the p-ch MOSFET is a voltage which causes a GIDL current of the n-ch MOSFET to be smaller than or equal to a predetermined value, and the low voltage applied to the source of the p-ch MOSFET is a voltage which causes a GIDL current of the p-ch MOSFET to be smaller than or equal to a predetermined value. ### Claim 5 (depends on 1) The switch circuit device according to claim 1, wherein, depending on the high- or low-level control voltage applied to the gate of the p-ch MOSFET, the voltage changing circuit applies a voltage which causes a sum of a GIDL current and a threshold current of the p-ch MOSFET to be smaller than or equal to a predetermined value, to a back gate of the p-ch MOSFET, and a voltage which causes a sum of a GIDL current and a threshold current of the n-ch MOSFET to be smaller than or equal to a predetermined value, to back gates of the plurality of n-ch MOSFETs. ### Claim 6 (depends on 1) The switch circuit device according to claim 1, wherein a resistor or an inductor is inserted in the gate of each of the n-ch MOSFET and the p-ch MOSFET. ### Claim 7 (depends on 1) The switch circuit device according to claim 1, wherein a resistor or an inductor is inserted in a back gate of each of the n-ch MOSFET and the p-ch MOSFET. ### Claim 8 A switch circuit comprising: a plurality of p-ch MOSFETs whose gates are connected together and whose drains and sources are connected in series; an n-ch MOSFET whose gate is connected to the gates of the plurality of p-ch MOSFETs and whose source is connected to the source and drain connected to each other of at least one pair of adjacent p-ch MOSFETs of the plurality of p-ch MOSFETs; an inverter for inverting and outputting a control voltage; and a voltage changing circuit for applying a high voltage to the drain of the n-ch MOSFET while a low-level control voltage inverted and output by the inverter is applied to the gate of the n-ch MOSFET, the high voltage being higher than the low-level control voltage, and a low voltage to the drain of the n-ch MOSFET while a high-level control voltage inverted and output by the inverter is applied to the gate of the n-ch MOSFET, the low voltage being lower than the high-level control voltage. ### Claim 9 (depends on 8) The switch circuit device according to claim 8, wherein the voltage changing circuit applies a control voltage to be input to the inverter, as it is, to the drain of the n-ch MOSFET. ### Claim 10 (depends on 8) The switch circuit device according to claim 8, wherein the low voltage applied to the drain of the n-ch MOSFET is 0 V. ### Claim 11 (depends on 8) The switch circuit device according to claim 8, wherein the low voltage applied to the drain of the n-ch MOSFET is a voltage which causes a GIDL current of the p-ch MOSFET to be smaller than or equal to a predetermined value, and the high voltage applied to the drain of the n-ch MOSFET is a voltage which causes a GIDL current of the n-ch MOSFET to be smaller than or equal to a predetermined value. ### Claim 12 (depends on 8) The switch circuit device according to claim 8, wherein, depending on the high- or low-level control voltage inverted and output by the inverter and applied to the gate of the n-ch MOSFET, the voltage changing circuit applies a voltage which causes a sum of a GIDL current and a threshold current of the n-ch MOSFET to be smaller than or equal to a predetermined value, to a back gate of the n-ch MOSFET, and a voltage which causes a sum of a GIDL current and a threshold current of the p-ch MOSFET to be smaller than or equal to a predetermined value, to back gates of the plurality of p-ch MOSFETs. ### Claim 13 (depends on 9) The switch circuit device according to claim 9, wherein the voltage changing circuit includes an even number of inverters connected in series for outputting the control voltage. ### Claim 14 (depends on 8) The switch circuit device according to claim 8, wherein a resistor or an inductor is inserted in the gates of the n-ch MOSFET and the p-ch MOSFET. ### Claim 15 (depends on 8) The switch circuit device according to claim 8, wherein a resistor or an inductor is inserted in back gates of the n-ch MOSFET and the p-ch MOSFET.