# US 7,746,150 B2 · Circuit and method for providing a fail-safe differential receiver

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- Number: US 7,746,150 B2
- Document ID: US7746150B2
- Status: Granted
- Kind: B2
- Application number: 11/493,253
- Filed: 2006-07-25
- Published: 2008-01-31
- Granted: 2010-06-29
- Earliest claimed: 2006-07-25
- Assignees: Micrel, Inc.
- Inventors: Thomas S. Wong; Uwe Biswurm; Bernd Neumann
- Web page: https://patentgrep.com/patent/US7746150B2

## CPC

- H03K 19/007: Fail-safe circuits
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

## Claims

### Claim 1

A fail-safe differential receiver circuit for use with a first differential input signal and a second differential input signal and at least one predetermined signal and a threshold voltage, the circuit comprising a differential amplifier configured to receive the first and second differential input signals, the differential amplifier generating first and second differential signals that are based on the first and second differential input signals and have a differential voltage, a peak detector coupled to the differential amplifier for generating a detect signal, a comparator coupled to the peak detector for comparing the detect signal to the threshold voltage and providing a comparison signal, and a directing circuit coupled to the differential amplifier for receiving the generated first and second differential signals and coupled to the comparator for receiving the comparison signal, the directing circuit selectively directing between the generated first and second differential signals and the at least one predetermined signal as a function of the value of the comparison signal from the comparator.

### Claim 2 (depends on 1)

The fail-safe differential receiver circuit of claim 1, wherein the differential amplifier comprises a first transistor for receiving the first differential input signal and a second transistor for receiving the second differential input signal.

### Claim 3 (depends on 2)

The fail-safe differential receiver circuit of claim 2, further comprising a first current source coupled to the first and second transistors.

### Claim 4 (depends on 3)

The fail-safe differential receiver circuit of claim 3, further comprising a second current source and a resistor coupled to the second current source for providing the threshold voltage.

### Claim 5 (depends on 4)

The fail-safe differential receiver circuit of claim 4, further comprising a third transistor coupled to the resistor and the second current source.

### Claim 6 (depends on 5)

The fail-safe differential receiver circuit of claim 5, wherein the peak detector includes a fourth transistor coupled to the first transistor and a fifth transistor coupled to the second transistor.

### Claim 7 (depends on 6)

The fail-safe differential receiver of claim 6, further comprising a third current source coupled to the fourth and fifth transistors.

### Claim 8 (depends on 7)

The fail-safe differential receiver circuit of claim 7, wherein the comparator includes a sixth transistor coupled to the third, fourth, and fifth transistors.

### Claim 9 (depends on 8)

The fail-safe differential receiver of claim 8, wherein the directing circuit includes a latch.

### Claim 10 (depends on 9)

The fail-safe differential receiver circuit of claim 9, wherein the latch includes a seventh transistor and an eighth transistor coupled to the sixth transistor.

### Claim 11 (depends on 10)

The fail-safe differential receiver circuit of claim 10, further comprising a ninth transistor and a tenth transistor coupled to the seventh and the eighth transistors.

### Claim 12 (depends on 11)

The fail-safe differential receiver circuit of claim 11, wherein the ninth transistor is coupled to the first transistor and the tenth transistor is coupled to the second transistor.

### Claim 13 (depends on 12)

The fail-safe differential receiver circuit of claim 12, wherein the ninth and tenth transistors are coupled to an output of the circuit.

### Claim 14 (depends on 1)

The fail-safe differential receiver circuit of claim 1, wherein the peak detector includes an integrating capacitor.

### Claim 15 (depends on 9)

The fail-safe differential receiver circuit of claim 9 for use with first and second earlier differential signals, wherein the latch includes a memory for retaining the first and second earlier differential signals and wherein the latch directs the first and second differential signals when the comparison signal is a first value and retains the first and second earlier differential signals as the at least one predetermined signal when the comparison signal is a second value.

### Claim 16 (depends on 1)

The fail-safe differential receiver of claim 1, wherein the directing circuit comprises a combination of logic gates for directing a high or low voltage signal as the at least one predetermined signal when the comparison signal is a second value.

### Claim 17

A fail-safe differential receiver circuit for use with a first differential input signal and a second differential input signal and at least one predetermined signal and a threshold voltage, the circuit comprising a first transistor coupled to the first differential input signal and a second transistor coupled to the second differential input signal for generating first and second differential signals that are based on the first and second differential input signals and have a differential voltage, a resistor coupled to a first current source for setting a threshold voltage, a third transistor coupled to the resistor and the first current source, a comparator coupled to the first, second, and third transistors for comparing the differential voltage to the threshold voltage and generating a comparison signal, and a fourth transistor and a fifth transistor coupled to the comparator for forming a directing circuit, the directing circuit selectively directing between the first and second differential signals and the at least one predetermined signal as a function of the value of the comparison signal from the comparator.

### Claim 18 (depends on 17)

The fail-safe differential receiver circuit of claim 17, further comprising a peak detector coupled to the first and second transistors.

### Claim 19 (depends on 18)

The fail-safe differential receiver circuit of claim 18, wherein the peak detector includes a sixth transistor coupled to the first transistor and a seventh transistor coupled to the second transistor.

### Claim 20 (depends on 19)

The fail-safe differential receiver circuit of claim 19, wherein the comparator includes an eighth transistor coupled to the sixth and seventh transistors.

### Claim 21 (depends on 17)

The fail-safe differential receiver circuit of claim 17, wherein the fourth and fifth transistors are coupled to a ninth transistor and a tenth transistor.

### Claim 22 (depends on 21)

The fail-safe differential receiver circuit of claim 21, wherein the ninth transistor is coupled to the first transistor and the tenth transistor is coupled to the second transistor.

### Claim 23 (depends on 22)

The fail-safe differential receiver of claim 22, wherein the ninth and tenth transistors are coupled to an output of the receiver.

### Claim 24 (depends on 18)

The fail-safe differential receiver of claim 18, wherein the peak detector further includes an integrating capacitor.

### Claim 25 (depends on 17)

The fail-safe differential receiver of claim 17, wherein the directing circuit comprises a latch.

### Claim 26 (depends on 17)

The fail-safe differential receiver of claim 17, wherein the directing circuit comprises a combination of logic gates for directing a high or low voltage signal as the at least one predetermined signal when the comparison signal indicates that the differential voltage is lower than the threshold voltage.

### Claim 27

A method for providing a fail-safe differential receiver, the method comprising generating a peak voltage signal amplitude from first and second differential signals that are based on a first differential input signal and a second differential input signal, comparing the peak voltage signal amplitude to a threshold voltage to generate a comparison signal and providing the comparison signal to a directing circuit, the directing circuit selectively directing between the first and second differential signals and at least one predetermined signal as a function of the comparison signal.

### Claim 28 (depends on 27)

The method of claim 27, further comprising generating the threshold voltage with a resistor coupled to a current source.

### Claim 29 (depends on 27)

The method of claim 27, further comprising determining the peak voltage signal amplitude with a peak detector.

### Claim 30 (depends on 28)

The method of claim 28, wherein comparing the peak voltage signal amplitude to the threshold voltage includes using a comparator coupled to the peak detector.

### Claim 31 (depends on 27)

The method of claim 27, wherein selectively directing includes enabling the directing circuit with the comparison signal when the generated peak voltage signal amplitude is higher than the threshold voltage.

### Claim 32 (depends on 27)

The method of claim 27, wherein selectively directing includes disabling the directing circuit with the comparison signal when the generated peak voltage signal amplitude is smaller than the threshold voltage.

### Claim 33 (depends on 27)

The method of claim 27, wherein the comparison signal is provided to a combination of logic gates for directing a high or low voltage signal as the at least one predetermined signal when the comparison signal indicates that the generated peak voltage signal amplitude is lower than the threshold voltage.