# US 7,746,149 B2 · Voltage level shift circuit and semiconductor integrated circuit

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- Number: US 7,746,149 B2
- Document ID: US7746149B2
- Status: Granted
- Kind: B2
- Application number: 12/484,664
- Filed: 2009-06-15
- Published: 2009-11-26
- Granted: 2010-06-29
- Earliest claimed: 2006-01-31
- Assignees: Seiko Instruments Inc.
- Inventors: Takashi Imura
- Web page: https://patentgrep.com/patent/US7746149B2

## CPC

- H03K 3/013: Modifications of generator to prevent operation by noise or interference
- H03K 3/35613: {the input circuit having a differential configuration}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M1) and an N-channel depletion type MOS transistor (M3); and a second voltage level shift circuit formed of a P-channel enhancement type transistor (M2) and an N-channel depletion type MOS transistor (M4). In the voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M5) is serially connected to the first voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M6) is serially connected to the second voltage level shift circuit, and a unit for complementarily controlling bias voltages of the respective cascode circuits. As a result, an output signal of the voltage level shift circuit connected to an input of a differential amplifier circuit, for expanding an input voltage range of a signal, is not affected by fluctuations in power supply voltage.

## Claims

### Claim 1

A voltage level shift circuit, comprising:
a first source follower circuit including:
a first P-channel enhancement type MOS transistor (M21), a gate terminal of which is connected to a first voltage signal input terminal (In11) and a drain terminal of which is grounded; and
a second P-channel enhancement type MOS transistor (M22), a drain terminal of which is connected to a source terminal of the first P-channel enhancement type MOS transistor (M21) and to a first voltage signal output terminal (Out11) to be a constant current load;
a second source follower circuit including:
a third P-channel enhancement type MOS transistor (M23), a gate terminal of which is connected to a second voltage signal input terminal (In12) and a drain terminal of which is grounded; and
a fourth P-channel enhancement type MOS transistor (M24), a drain terminal of which is connected to a source terminal of the third P-channel enhancement type MOS transistor (M23) and to a second voltage signal output terminal (Out12) to be a constant current load;
a cascode circuit formed of an N-channel depletion type MOS transistor (M26), a gate terminal of which is connected to a fixed potential, a source terminal of which is connected to a source terminal of the second P-channel enhancement type MOS transistor (M22) and to a source terminal of the fourth P-channel enhancement type MOS transistor (M24), and a drain terminal of which is fixed to power supply voltage; and
a fifth P-channel enhancement type MOS transistor (M25) which, together with the second P-channel enhancement type MOS transistor (M22) and the fourth P-channel enhancement type MOS transistor (M24), forms a current mirror circuit, for causing a current which is the same as a reference current (Iref) to flow through the second P-channel enhancement type MOS transistor (M22) and the fourth P-channel enhancement type MOS transistor (M24).

### Claim 2 (depends on 1)

A semiconductor integrated circuit, comprising the voltage level shift circuit according to claim 1.