# US 7,746,146 B2 · Junction field effect transistor input buffer level shifting circuit

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- Number: US 7,746,146 B2
- Document ID: US7746146B2
- Status: Granted
- Kind: B2
- Application number: 11/515,252
- Filed: 2006-09-01
- Published: 2008-02-21
- Granted: 2010-06-29
- Earliest claimed: 2006-09-01
- Assignees: SuVolta, Inc.
- Inventors: Richard K. Chou; Damodar R. Thummalapally
- Web page: https://patentgrep.com/patent/US7746146B2

## CPC

- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03K 3/356034: {the input circuit having a differential configuration}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.

## Claims

### Claim 1

A method of interfacing between a first semiconductor device including junction field effect transistors (JFETs) and a bus, comprising the steps of:
receiving an input signal having a first voltage swing at an input terminal of the first semiconductor device including JFETs;
translating the input signal to an internal signal having a second voltage swing lower than the first voltage swing;
providing the input signal onto the bus from a second semiconductor device operating at a second power supply voltage higher than a first power supply voltage at which the first semiconductor device operates;
receiving the internal signal by core circuitry including JFETs and operating at a first power supply voltage;
providing a second internal signal having essentially the second voltage swing from the core circuitry; and
translating the second internal signal to an output signal having essentially the first voltage swing.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the first voltage swing is substantially greater than the second voltage swing.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
the first power supply voltage is essentially the same value as the second voltage swing.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
the second voltage swing is about 0.5 volts.

### Claim 5 (depends on 1)

The method of claim 1, further including:
providing the input signal onto the bus from a second semiconductor device operating at a second power supply voltage higher than a first power supply voltage at which the first semiconductor device operates.

### Claim 6

A system, comprising:
at least a first semiconductor device, comprising
an input buffer including at least one junction field effect transistor (JFET), the input buffer receiving an input signal having a first voltage swing and providing a shifted signal having a second voltage swing lower than the first voltage swing; and
core circuitry comprising JFETs, the core circuitry coupled to receive the shifted signal wherein the core circuitry operates from a first power supply having a magnitude less than the first voltage swing; and
an output buffer including at least one JFET, the output buffer coupled to receive a first signal having essentially the second voltage swing from the core circuitry and providing an output signal having essentially the first voltage swing.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein:
the first semiconductor device further includes a higher voltage section coupled to and formed in the same substrate as the output buffer, the higher voltage section operating at a power supply level greater than the first power supply.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein:
the higher voltage section comprises insulated gate field effect transistors (IGFETs).

### Claim 9 (depends on 6)

The system of claim 6, further including:
at least a second semiconductor device coupled to the output buffer of the first semiconductor device by at least one signal line, the second semiconductor device operating at a power supply level greater than the first power supply.

### Claim 10 (depends on 6)

The system of claim 6, further including:
the first power supply has a magnitude of less than a forward bias voltage of a pn junction formed by at least one of the JFETs in the core circuitry and the core circuitry includes complementary JFETs.

### Claim 11 (depends on 6)

The system of claim 6, further including:
at least a second semiconductor device coupled to the input buffer of the first semiconductor device by at least one signal line, the second semiconductor device operating at a power supply level greater than the first power supply.

### Claim 12 (depends on 6)

The semiconductor device of claim 6, wherein:
the first semiconductor device further includes a higher voltage section formed in the same substrate as the input buffer circuit and coupled thereto, the higher voltage section operating at a power supply level greater than the first power supply.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein:
the higher voltage section comprises insulated gate field effect transistors (IGFETs).