# US 7,746,145 B2 · Level shift circuit capable of preventing occurrence of malfunction when low power supply fluctuates, and semiconductor integrated circuit including the circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,145 B2 - Document ID: US7746145B2 - Status: Granted - Kind: B2 - Application number: 10/949,689 - Filed: 2004-09-24 - Published: 2007-10-04 - Granted: 2010-06-29 - Earliest claimed: 2003-09-25 - Assignees: Ricoh Company, Ltd. - Inventors: Kazuya Nishimura - Web page: https://patentgrep.com/patent/US7746145B2 ## CPC - H03K 3/013: Modifications of generator to prevent operation by noise or interference - H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A level shift circuit includes two high-voltage PMOS, two high-voltage NMOS, and two low-voltage NMOS transistors. The first high-voltage PMOS is connected between a high voltage and a second output terminal, having a gate connected to a first output terminal. The second high-voltage PMOS is connected between the high voltage and the first terminal, having a gate connected to the second terminal. The first high-voltage NMOS is connected to the second terminal, having a gate through which a second signal is input. The first low-voltage NMOS is connected between the first high-voltage N-channel MOS and a ground, having a gate through which the second signal is input. The second high-voltage NMOS is connected to the first terminal, having a gate through which a first signal is input. The second low-voltage NMOS is connected between the second N-channel MOS and the ground, having a gate through which the first signal is input. ## Claims ### Claim 1 A level shill circuit having a first power voltage and a second power voltage greater than the first power voltage, the level shill circuit comprising: a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage; a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal; a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal; a first high-withstand-voltage N-channel MOS transistor having a drain connected to the second output terminal and a source connected directly to a ground, and having a gate through which the second input signal is input; a second high-withstand-voltage N-channel MOS depletion-type transistor connected to the first output terminal and having a gate through which the first input signal is input; and a second low-withstand-voltage N-channel MOS transistor connected between the second N-channel MOS depiction-type transistor and the ground and having a gate through which the first input signal is input, wherein the second high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts. ### Claim 2 (depends on 1) A level shift circuit of claim 1, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the second high-withstand-voltage N-channel MOS depletion-type transistor has a withstand voltage greater than the second power voltage, and each of the first high-withstand-voltage N-channel MOS transistor and the second low-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage. ### Claim 3 (depends on 1) A level shift circuit of claim 1, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the second high-withstand-voltage N-channel MOS depletion-type transistors has a withstand voltage greater than the second power voltage, and the second low-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage and smaller than the second power voltage. ### Claim 4 (depends on 1) The level shift circuit of claim 1, wherein the source of the first high-withstand-voltage N-channel MOS transistor has a potential of approximately 0 volts. ### Claim 5 (depends on 1) The level shill circuit of claim 1, wherein there are no transistors connected between the source of the first high-withstand-voltage N-channel MOS transistor and the ground. ### Claim 6 (depends on 1) The level shift circuit of claim 1, wherein there is no potential drop between the source of the first high-withstand-voltage N-channel MOS transistor and the ground. ### Claim 7 A level shift circuit having a first power voltage and a second power voltage greater than the first power voltage, the level shift circuit comprising: a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage; a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal; a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal; a first high-withstand-voltage N-channel MOS depletion-type transistor connected to the second output terminal and having a gate through which the second input signal is input; a first low-withstand-voltage N-channel MOS transistor connected between the first high-withstand-voltage N-channel MOS depletion-type transistor and a ground and having a gate through which the second input signal is input; and a second high-withstand-voltage N-channel MOS transistor having a drain connected to the first output terminal and a source connected directly to the ground, and having a gate through which the first input signal is input, wherein the first high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts. ### Claim 8 (depends on 7) A level shift circuit of claim 7, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the first high-withstand-voltage N-channel MOS depletion-type transistors has a withstand voltage greater than the second power voltage, and each of the first low-withstand-voltage N-channel MOS transistor and the second high-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage. ### Claim 9 (depends on 7) A level shift circuit of claim 7, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the first high-withstand-voltage N-channel MOS depletion-type transistors has a withstand voltage greater than the second power voltage, and the first-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage and smaller than the second power voltage. ### Claim 10 A semiconductor integrated circuit having a first power voltage and a second power voltage greater than the first power voltage, the semiconductor integrated circuit comprising: a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage; a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal; a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal; a first high-withstand-voltage N-channel MOS transistor having a drain connected to the second output terminal and a source connected directly to a ground, and having a gate through which the second input signal is input; a second high-withstand-voltage N-channel MOS depletion-type transistor connected to the first output terminal and having a gate through which the first input signal is input; and a second low-withstand-voltage N-channel MOS transistor connected between the second N-channel MOS depletion-type transistor and the ground and having a gate through which the first input signal is input, wherein the second high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts. ### Claim 11 (depends on 10) A semiconductor integrated circuit of claim 10, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the second high-withstand-voltage N-channel MOS depletion-type transistor has a withstand voltage greater than the second power voltage, and each of the first high-withstand-voltage N-channel MOS transistor and the second low-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage. ### Claim 12 (depends on 10) A semiconductor integrated circuit of claim 10, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the second high-withstand-voltage N-channel MOS depletion-type transistors has a withstand voltage greater than the second power voltage, and the second low-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage and smaller than the second power voltage. ### Claim 13 A semiconductor integrated circuit having a first power voltage and a second power voltage greater than the first power voltage, the semiconductor integrated circuit comprising: a differential circuit pulled up to the first power voltage and configured to convert a signal into a differential pair of first and second input signals alternatingly changing in amplitude within the first power voltage; a first high-withstand-voltage P-channel MOS transistor connected between the second power voltage and a second output terminal and having a gate connected to a first output terminal; a second high-withstand-voltage P-channel MOS transistor connected between the second power voltage and the first output terminal and having a gate connected to the second output terminal; a first high-withstand-voltage N-channel MOS depletion-type transistor connected to the second output terminal and having a gate through which the second input signal is input; a first low-withstand-voltage N-channel MOS transistor connected between the first high-withstand-voltage N-channel MOS depletion-type transistor and a ground and having a gate through which the second input signal is input; and a second high-withstand-voltage N-channel MOS transistor having a drain connected to the first output terminal and a source connected directly to the ground, and having a gate through which the first input signal is input; wherein the first high-withstand-voltage N-channel MOS depletion-type transistor has a threshold voltage less than 0 volts. ### Claim 14 (depends on 13) A semiconductor integrated circuit of claim 13, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the first high-withstand-voltage N-channel MOS depletion-type transistors has a withstand voltage greater than the second power voltage, and each of the first low-withstand-voltage N-channel MOS transistor and the second high-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage. ### Claim 15 (depends on 13) A semiconductor integrated circuit of claim 13, wherein each of the first and second high-withstand-voltage P-channel MOS transistors and the first high-withstand-voltage N-channel MOS depletion-type transistors has a withstand voltage greater than the second power voltage, and the first low-withstand-voltage N-channel MOS transistor has a withstand voltage greater than the first power voltage and smaller than the second power voltage.