# US 7,746,141 B2 · Delay circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,141 B2 - Document ID: US7746141B2 - Status: Granted - Kind: B2 - Application number: 11/759,309 - Filed: 2007-06-07 - Published: 2007-12-27 - Granted: 2010-06-29 - Earliest claimed: 2006-06-26 - Assignees: NEC Electronics Corporation - Inventors: Hiroyuki Takahashi - Web page: https://patentgrep.com/patent/US7746141B2 ## CPC - H03H 11/265: {with adjustable delay} - H03K 5/133: using a chain of active delay devices - H03K 2005/0013: {Avoiding variations of delay due to power supply} - H03K 2005/00143: {Avoiding variations of delay due to temperature} - H03K 2005/00195: {using FET's} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A delay circuit includes a delay time setting circuit to set a delay time of an output signal with respect to an input signal, a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input terminal of the delay time setting circuit and a second transistor connected to an output terminal of the delay time setting circuit and configured to reset the output terminal of the delay time setting circuit to a second voltage and clear the reset of the output terminal of the delay time setting circuit after the first voltage is set. ## Claims ### Claim 1 A delay circuit comprising: a delay time setting circuit to delay a signal input to an input terminal and output the signal as an output signal to an output terminal, wherein an output of a single first transistor is connected to an input of the delay time setting circuit to set a first voltage of said delay time setting circuit or to set an open state of said delay time setting circuit, according to a conduction state of said single first transistor, and an output of the delay time setting circuit is set to a second voltage or an open state according to a conduction state of another transistor of an opposite conductivity type to the first transistor, wherein a control terminal of a first transistor of a delay circuit in a second and subsequent stages among a plurality of delay circuits connected in series is connected to an input terminal of the delay time setting circuit in a previous stage, and a control terminal of a second transistor of the delay circuit in the second and subsequent stages is connected to an output terminal of the delay time setting circuit in a previous stage. ### Claim 2 (depends on 1) The delay circuit according to claim 1, wherein the delay time setting circuit comprises: a resistor; and a capacitor element having a capacitance value being variable according to a voltage of a connection point with the resistor. ### Claim 3 (depends on 2) The delay circuit according to claim 2, wherein the delay time setting circuit comprises: a switch to change a resistance value of the resistor. ### Claim 4 (depends on 2) The delay circuit according to claim 2, wherein the capacitor element is a transistor which has an opposite conductivity type of the single first transistor. ### Claim 5 (depends on 4) The delay circuit according to claim 4, wherein drain and source of the capacitor element are coupled to the second voltage. ### Claim 6 (depends on 1) The delay circuit according to claim 1, wherein the delay circuit delays either one of a rising edge and a falling edge of an input signal. ### Claim 7 (depends on 1) The delay circuit according to claim 1, wherein in a subsequent stage of a delay circuit to generate a first output signal by delaying a falling edge of an input signal, a delay circuit to generate a second output signal by delaying a rising edge of the first output signal is connected. ### Claim 8 (depends on 1) The delay circuit according to claim 1, wherein the delay circuit is used as one of circuits in a volatile semiconductor memory. ### Claim 9 A delay circuit comprising: a delay time setting circuit to set a delay time of an output signal with respect to an input signal; a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input terminal of the delay time setting circuit; and a second transistor connected to an output terminal of the delay time setting circuit and configured to reset the output terminal of the delay time setting circuit to a second voltage and clear the reset of the output terminal of the delay time setting circuit after the first voltage is set, wherein a signal generated by the same signal source is input to a control terminal of the first transistor and a control terminal of the second transistor of a delay circuit in a first stage among a plurality of delay circuits connected in series, wherein the first and the second transistors of the delay circuit in the first stage among a plurality of delay circuits connected in series have a lower threshold voltage than that of a standard transistor in a manufacturing process. ### Claim 10 A delay circuit comprising: a delay time setting circuit to delay a signal input to an input terminal and output the signal as an output signal to an output terminal, wherein an input of the delay time setting circuit is set to a first voltage or an open state without using a transistor of a first conductivity type, according to a conduction state of a first transistor of a second conductivity type opposite to the first conductivity type, and an output of the delay time setting circuit is set to a second voltage or an open state according to a conduction state of a second transistor of an opposite conductivity type to the first transistor, wherein the delay circuit is composed of a plurality of delay circuits connected with each other, and an output of a delay circuit in one stage is not input to the delay time setting circuit of a delay circuit in a subsequent stage and is connected to a gate of the second transistor of the delay circuit in the subsequent stage.