# US 7,746,140 B2 · Scannable latch

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- Number: US 7,746,140 B2
- Document ID: US7746140B2
- Status: Granted
- Kind: B2
- Application number: 11/550,997
- Filed: 2006-10-19
- Published: 2007-04-05
- Granted: 2010-06-29
- Earliest claimed: 2004-11-05
- Assignees: International Business Machines Corporation
- Inventors: Sang Hoo Dhong; Joel A. Silberman; Osamu Takahashi
- Web page: https://patentgrep.com/patent/US7746140B2

## CPC

- H03K 3/356113: {using additional transistors in the input circuit}
- G01R 31/318541: {Scan latches or cell details}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.

## Claims

### Claim 1

A scannable latch comprising:
a dynamic circuit;
a first latch for providing a data out signal from a data in signal; and
a second latch having two NAND gates coupled to said dynamic circuit and a pair of transfer gates coupled to said two NAND gates for providing a scan out signal from a scan input signal.

### Claim 2 (depends on 1)

The scannable latch of claim 1, wherein said dynamic circuit includes a precharge transistor and a pull-down network.

### Claim 3 (depends on 1)

The scannable latch of claim 1, wherein an output of a first one of said two NAND gates is connected to a first input of a second one of said two NAND gates, and an output of said second one of said two NAND gates is connected to a first input of said first one of said two NAND gates during a normal mode.

### Claim 4 (depends on 3)

The scannable latch of claim 3, wherein said two NAND gates become inverters when second inputs of said two NAND gates are held at a logic high during a scan mode.

### Claim 5 (depends on 1)

The scannable latch of claim 1, wherein said scannable latch generates an output at said first one of said two NAND gates.

### Claim 6 (depends on 1)

The scannable latch of claim 1, wherein said scan input signal is provided to said transfer gates via an L1 latch.

### Claim 7 (depends on 1)

The scannable latch of claim 1, wherein said transfer gates are being toggled during a scan mode.