# US 7,746,139 B2 · Radiation hardened D-type flip flop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,139 B2 - Document ID: US7746139B2 - Status: Granted - Kind: B2 - Application number: 12/056,455 - Filed: 2008-03-27 - Published: 2008-09-04 - Granted: 2010-06-29 - Earliest claimed: 2006-05-18 - Assignees: International Business Machines Corporation - Inventors: William Yeh-Yung Mo - Web page: https://patentgrep.com/patent/US7746139B2 ## CPC - H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - H03K 19/0033: {Radiation hardening} - H03K 23/002: {using semiconductor devices (H03K23/78, H03K23/80, H03K23/84 take precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A programmable phase frequency divider for space applications is implemented in CMOS technology, and includes a number of radiation hardened D-type flip flops. The radiation hardened D-type flip flop circuits are designed to keep running properly at GHz frequencies in the presence of single event upset (SEU) hits. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs and each consists of a master latch and a slave latch connected in tandem. The master and slave latches each consist of two latch half circuits having dual complementary inputs and outputs that are mutually interconnected in a dual interlocked cell (DICE) configuration, with the result that the D-type flip flop is immune to an SEU affecting at most one of the flip flop's four dual complementary data inputs. ## Claims ### Claim 1 A radiation hardened D-type flip flop comprising: a master latch having a clock input, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs; and a slave latch having first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs, wherein the first data output and the first complementary data output of the master latch are connected respectively to the first data input and the first complementary data input of the slave latch, wherein the second data output and the second complementary data output of the master latch are connected respectively to the second data input and the second complementary data input of the slave latch, wherein the master latch comprises two identical master latch half circuits, the master latch half circuits having respective dual complementary inputs and outputs through which the master latch half circuits are mutually interconnected, and wherein the slave latch comprises two identical slave latch half circuits, different from the master latch half circuits, the slave latch half circuits having respective dual complementary inputs and outputs through which the slave latch half circuits are mutually interconnected. ### Claim 2 (depends on 1) The D-type flip flop of claim 1, wherein the D-type flip flop is configured to operate, in the absence of single event upsets, with the first and second data inputs having nominally a same first input voltage level and the first and second complementary data inputs having nominally a same second input voltage level which is complementary to the first input voltage level. ### Claim 3 (depends on 1) The D-type flip flop of claim 1, wherein operation of the D-type flip flop is immune to a single event upset affecting at most one of the four complementary data inputs. ### Claim 4 (depends on 1) The D-type flip flop of claim 1, wherein the master latch and the slave latch are implemented in CMOS technology. ### Claim 5 A radiation hardened D-type flip flop comprising: a master latch having a clock input, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs; and a slave latch having first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs, wherein the first data output and the first complementary data output of the master latch are connected respectively to the first data input and the first complementary data input of the slave latch, wherein the second data output and the second complementary data output of the master latch are connected respectively to the second data input and the second complementary data input of the slave latch, and wherein the master latch comprises: a first master latch half circuit having a clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output; and a second master latch half circuit identical to the first master latch half circuit and having a clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output, wherein the respective clock inputs of the first and second master latch half circuits are connected together in parallel, the respective first and second data inputs and first and second complementary data inputs of the first and second master latch half circuits are connected together in parallel, the data output and the complementary data output of the first master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second master latch half circuit, and the data output and the complementary data output of the second master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the first master latch half circuit. ### Claim 6 (depends on 5) The D-type flip flop of claim 5, wherein the slave latch comprises: a first slave latch half circuit having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output; and a second slave latch half circuit identical to the first slave latch half circuit and having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output, wherein the first data input and the first complementary data input of the first slave latch half circuit are respective connected in parallel with the second data input and the second complementary data input of the second slave latch half circuit, the second data input and the second complementary data input of the first slave latch half circuit are respectively connected in parallel with the first data input and the first complementary data input of the second slave latch half circuit, the data output and the complementary data output of the first slave latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second slave latch half circuit, and the data output and the complementary data output of the second slave latch half circuit are connected respectively to the feedback input and complementary feedback input of the first slave latch half circuit. ### Claim 7 (depends on 5) The D-type flip flop of claim 5, wherein the D-type flip flop is configured to operate, in the absence of single event upsets, with the first and second data inputs having nominally a same first input voltage level and the first and second complementary data inputs having nominally a same second input voltage level which is complementary to the first input voltage level. ### Claim 8 (depends on 5) The D-type flip flop of claim 5, wherein operation of the D-type flip flop is immune to a single event upset affecting at most one of the four complementary data inputs. ### Claim 9 (depends on 5) The D-type flip flop of claim 5, wherein the master latch and the slave latch are implemented in CMOS technology. ### Claim 10 A radiation hardened D-type flip flop comprising: a master latch having a clock input, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs; and a slave latch having first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs, wherein the first data output and the first complementary data output of the master latch are connected respectively to the first data input and the first complementary data input of the slave latch, wherein the second data output and the second complementary data output of the master latch are connected respectively to the second data input and the second complementary data input of the slave latch, and wherein the slave latch comprises: a first slave latch half circuit having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output; and a second slave latch half circuit identical to the first slave latch half circuit and having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output, wherein the first data input and the first complementary data input of the first slave latch half circuit are respective connected in parallel with the second data input and the second complementary data input of the second slave latch half circuit, the second data input and the second complementary data input of the first slave latch half circuit are respectively connected in parallel with the first data input and the first complementary data input of the second slave latch half circuit, the data output and the complementary data output of the first slave latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second slave latch half circuit, and the data output and the complementary data output of the second slave latch half circuit are connected respectively to the feedback input and complementary feedback input of the first slave latch half circuit. ### Claim 11 (depends on 10) The D-type flip flop of claim 10, wherein the master latch and the slave latch are implemented in CMOS technology.