# US 7,746,138 B2 · Semiconductor integrated circuit with flip-flop circuits mounted thereon

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- Number: US 7,746,138 B2
- Document ID: US7746138B2
- Status: Granted
- Kind: B2
- Application number: 12/044,406
- Filed: 2008-03-07
- Published: 2008-09-11
- Granted: 2010-06-29
- Earliest claimed: 2007-03-07
- Assignees: Sanyo Electric Co., Ltd.
- Inventors: Satoru Sekine; Yoshitaka Ueda; Takashi Asano; Shinji Furuichi; Atsushi Wada
- Web page: https://patentgrep.com/patent/US7746138B2

## CPC

- H03K 3/35625: {using complementary field-effect transistors}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.

## Claims

### Claim 1

A semiconductor integrated circuit including a first flip-flop circuit and a second flip-flop circuit, having different circuit configurations, which perform an identical digital signal processing, wherein the first and second flip-flop circuits are mixed on a single semiconductor substrate, and wherein,
each of the first and second flip-flop circuits includes a clocked inverter, and wherein
the size of a transistor, included in the clocked inverter of the second flip-flop circuit, in which conduction or nonconduction is controlled by a clock signal is set to be smaller than the size of a transistor, included in the inverter of the first flip-flop circuit, in which conduction or nonconduction is controlled by the clock signal.

### Claim 2 (depends on 1)

A semiconductor integrated circuit, according to claim 1, including a plurality of the second flip-flop circuits,
wherein an external clock signal, supplied externally, with an equal delay time is inputted to each of the plurality of the second flip-flop circuits.

### Claim 3 (depends on 2)

A semiconductor integrated circuit according to claim 2, wherein the external clock signal is supplied via a path wired by a clock tree scheme.