# US 7,746,135 B2 · Wake-up circuit

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- Number: US 7,746,135 B2
- Document ID: US7746135B2
- Status: Granted
- Kind: B2
- Application number: 11/864,923
- Filed: 2007-09-29
- Published: 2009-04-02
- Granted: 2010-06-29
- Earliest claimed: 2007-09-29
- Assignees: Intel Corporation
- Inventors: Jacob S. Schneider; Navneet Dour; Harishankar Sridharan
- Web page: https://patentgrep.com/patent/US7746135B2

## CPC

- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)}
- H03L 7/0805: {the loop being adapted to provide an additional control signal for use outside the loop}
- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- H03L 7/10: for assuring initial synchronisation or for broadening the capture range
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.

## Claims

### Claim 1

A DLL circuit, comprising:
a wake-up circuit to couple a bias input node to a voltage level that is higher then a control bias node in response to a wake-up event and to couple the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another, the wake-up circuit comprising a comparator with inputs coupled to the bias input node and control bias node and an output coupled to a pull-up transistor, a pass gate coupled between the bias input node and control bias node, and a logic gate coupled between the comparator output and the pass gate to turn on the pass gate when the voltage levels at the bias input and control bias nodes are sufficiently close.

### Claim 2 (depends on 1)

The DLL circuit of claim 1, in which the logic gate is an AND gate.

### Claim 3 (depends on 1)

The DLL circuit of claim 1, in which the pull-up transistor is a PMOS transistor.

### Claim 4 (depends on 1)

The DLL circuit of claim 1, in which a wake-up signal is coupled to the logic gate to turn off the pass gate for a power down mode.

### Claim 5 (depends on 1)

The DLL circuit of claim 1, in which the control bias node comes from a bias replica circuit that replicates a bias signal of a Master DLL circuit.

### Claim 6

A DLL circuit, comprising:
a master DLL circuit to provide a control bias signal to control a slave circuit through a slave bias node; and
a wake-up circuit having (i) a comparator with inputs coupled to the control bias signal and the slave bias node, the comparator having an output coupled to a pull-up transistor, (ii) a pass gate coupled between the control bias signal and slave bias node, and (iii) a logic gate coupled between the comparator output and the pass gate to turn on the pass gate when the voltage level of the control bias signal is sufficiently close to the voltage level at the slave bias node.

### Claim 7 (depends on 6)

The DLL circuit of claim 6, in which the logic gate is an AND gate.

### Claim 8 (depends on 6)

The DLL circuit of claim 6, in which the pull-up transistor is a PMOS transistor.

### Claim 9 (depends on 6)

The DLL circuit of claim 6, in which a wake-up signal is coupled to the logic gate to turn off the pass gate for a power down mode.

### Claim 10 (depends on 6)

The DLL circuit of claim 6, in which the control bias signal comes from a bias replica circuit that replicates a bias signal of a Master DLL circuit.