# US 7,746,133 B2 · Charge pump circuit

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- Number: US 7,746,133 B2
- Document ID: US7746133B2
- Status: Granted
- Kind: B2
- Application number: 12/064,374
- Filed: 2006-09-08
- Published: 2008-09-18
- Granted: 2010-06-29
- Earliest claimed: 2005-09-08
- Assignees: Sony United Kingdom Limited
- Inventors: Peter William Gaussen
- Web page: https://patentgrep.com/patent/US7746133B2

## CPC

- H03L 7/0895: {Details of the current generators (H03L7/0893 takes precedence)}
- H03L 7/1974: {for fractional frequency division}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A charge pump circuit including an input rail, an output rail, a voltage rail, a control line, an MOS input transistor including a gate and a channel connected between the input rail and the voltage rail, and an MOS output transistor including a gate and a channel connected between the output rail and the voltage rail. The gate of the input transistor is connected to the gate of the output transistor and a switch connects the channel of the output transistor to the voltage rail in response to a signal on the control line. The channel of an input cascode transistor connects the channel of the input transistor to the input rail and the channel of an output cascode transistor connects the channel of the output transistor to the output rail. The gate of the input cascode transistor is connected to the gate of the output cascode transistor.

## Claims

### Claim 1

A charge pump circuit comprising:
an input rail;
an output rail;
a voltage rail;
a control line;
an MOS input transistor, the input transistor including a channel and a gate, the channel of the input transistor being connected between the input rail and the voltage rail;
an MOS output transistor, the output transistor including a channel and a gate, the channel of the output transistor being connected between the output rail and the voltage rail, the gate of the input transistor being connected to the gate of the output transistor;
a switch for connecting the channel of the output transistor to the voltage rail in response to a signal on the control line;
an MOS input cascode transistor, the input cascode transistor including a channel and a gate, the channel of the input cascode transistor connecting the channel of the input transistor to the input rail;
an MOS output cascode transistor, the output cascode transistor including a channel and a gate, the channel of the output cascode transistor connecting the channel of the output transistor to the output rail, the gate of the input cascode transistor being connected to the gate of the output cascode transistor; and
a switched bias circuit connected between the gate of the output cascode transistor and the voltage rail for biasing the voltage of the gate of the output cascode transistor in response to an absence of the signal on the control line such that the output cascode transistor inhibits flow of current through the output transistor from the output rail; wherein
closing and opening the switch allows current to flow and not flow respectively between the output rail and the output transistor.

### Claim 2 (depends on 1)

A charge pump circuit according to claim 1 wherein:
the bias circuit includes an MOS switch transistor, the switch transistor including a channel and a gate, the channel of the switch transistor being connected in series with a bias element providing a voltage drop, the gate of the switch transistor being controlled by a voltage responsive to the signal on the control line.

### Claim 3 (depends on 2)

A charge pump circuit according to claim 2 wherein:
the bias circuit includes an inverter connecting the gate of the switch transistor to the control line.

### Claim 4 (depends on 3)

A charge pump circuit according to claim 3, further comprising:
a bias resistor connecting the inverter to the gate of the switch transistor.

### Claim 5 (depends on 2)

A charge pump circuit according to claim 2 wherein:
the bias element includes an MOS bias transistor, the bias transistor including a channel and a gate, the channel of the bias transistor connecting the switch transistor to the voltage line and the gate of the bias transistor being connected between the channel of the bias transistor and the channel of the switch transistor.

### Claim 6 (depends on 1)

A charge pump circuit according to claim 1 wherein:
the switch is an MOS control transistor, the control transistor including a channel and a gate, the channel of the control transistor being connected between the voltage rail and the output transistor, and the gate of the control transistor being connected to the control line.

### Claim 7 (depends on 6)

A charge pump circuit according to claim 6, further comprising:
a switch resistor connecting the control line to the gate of the control transistor.

### Claim 8 (depends on 6)

A charge pump circuit according to claim 6, further comprising:
an MOS compensation transistor, the compensation transistor including a channel and a gate, the channel of the compensation transistor connecting the input transistor to the voltage rail, and the gate of the compensation transistor being held at a fixed voltage.

### Claim 9 (depends on 1)

A charge pump circuit according to claim 1, further comprising:
a cascode switch responsive to the signal on the control line to connect the gate of the input cascode transistor to the gate of the output cascode transistor.

### Claim 10 (depends on 9)

A charge pump circuit according to claim 9, wherein:
the cascode switch includes an MOS cascode control transistor, the cascode control transistor including a channel and a gate, the channel of the cascode control transistor being connected between the gate of the input cascode transistor and the gate of the output cascode transistor, and the gate of the cascode control transistor being connected to the control line.

### Claim 11 (depends on 10)

A charge pump circuit according to claim 10, further comprising:
a cascode resistor connecting the control line to the gate of the cascode control transistor.

### Claim 12

A charge pump for use in a fractional-N frequency synthesizer, the charge pump comprising:
a first charge pump circuit including:
an input rail;
an output rail;
a voltage rail;
a control line;
an MOS input transistor, the input transistor including a channel and a gate, the channel of the input transistor being connected between the input rail and the voltage rail;
an MOS output transistor, the output transistor including a channel and a gate, the channel of the output transistor being connected between the output rail and the voltage rail, the gate of the input transistor being connected to the gate of the output transistor;
a switch for connecting the channel of the output transistor to the voltage rail in response to a signal on the control line;
an MOS input cascode transistor, the input cascode transistor including a channel and a gate, the channel of the input cascode transistor connecting the channel of the input transistor to the input rail;
an MOS output cascode transistor, the output cascode transistor including a channel and a gate, the channel of the output cascode transistor connecting the channel of the output transistor to the output rail, the gate of the input cascode transistor being connected to the gate of the output cascode transistor; and
a switched bias circuit connected between the gate of the output cascode transistor and the voltage rail for biasing the voltage of the gate of the output cascode transistor in response to an absence of the signal on the control line such that the output cascode transistor inhibits flow of current through the output transistor from the output rail;
wherein closing and opening said switch allows current to flow and not flow respectively between the output rail and the output transistor and wherein n-MOS transistors are used for pump down; and
a second charge pump circuit including:
an input rail;
an output rail;
a voltage rail;
a control line;
an MOS input transistor, the input transistor including a channel and a gate, the channel of the input transistor being connected between the input rail and the voltage rail;
an MOS output transistor, the output transistor including a channel and a gate, the channel of the output transistor being connected between the output rail and the voltage rail, the gate of the input transistor being connected to the gate of the output transistor;
a switch for connecting the channel of the output transistor to the voltage rail in response to a signal on the control line;
an MOS input cascode transistor, the input cascode transistor including a channel and a gate, the channel of the input cascode transistor connecting the channel of the input transistor to the input rail;
an MOS output cascode transistor, the output cascode transistor including a channel and a gate, the channel of the output cascode transistor connecting the channel of the output transistor to the output rail, the gate of the input cascode transistor being connected to the gate of the output cascode transistor; and
a switched bias circuit connected between the gate of the output cascode transistor and the voltage rail for biasing the voltage of the gate of the output cascode transistor in response to an absence of the signal on the control line such that the output cascode transistor inhibits flow of current through the output transistor from the output rail;
wherein closing and opening the switch allows current to flow and not flow respectively between the output rail and the output transistor, and wherein p-MOS transistors are used for pump up to complement the first charge pump circuit using n-MOS transistors.

### Claim 13 (depends on 12)

A fractional-N frequency synthesizer comprising:
a voltage controlled oscillator;
a fractional N divider connected to the output of the voltage controlled oscillator and providing a divided signal;
a phase comparator for comparing the divided signal with a reference signal and providing a comparison output;
a charge pump according to claim 12 for receiving the comparison output as an input and providing pump down and pump up outputs; and
a filter for filtering a sum of the pump down and pump up outputs and providing the filtered sum as an input to the voltage controlled oscillator.

### Claim 14 (depends on 13)

An integrated circuit including a fractional N-frequency synthesizer according to claim 13.

### Claim 15 (depends on 14)

An integrated circuit according to claim 14 which is a quad band transceiver integrated circuit.

### Claim 16 (depends on 14)

An integrated circuit according to claim 14 which is a television tuner integrated circuit.

### Claim 17 (depends on 13)

A mobile telephone including a fractional N-frequency synthesizer according to claim 13.

### Claim 18 (depends on 13)

A television receiving including a fractional-N frequency synthesizer according to claim 13.

### Claim 19 (depends on 12)

An integrated circuit including a charge pump according to claim 12.

### Claim 20 (depends on 19)

An integrated circuit according to claim 19 which is a quad band transceiver integrated circuit.

### Claim 21 (depends on 19)

An integrated circuit according to claim 19 which is a television tuner integrated circuit.

### Claim 22 (depends on 12)

A mobile telephone including a charge pump according to claim 12.

### Claim 23 (depends on 12)

A television receiver including a charge pump according to claim 12.

### Claim 24

A charge pump circuit comprising:
an input rail;
an output rail;
a voltage rail;
a control line;
an MOS input transistor, the input transistor including a channel and a gate, the channel of the input transistor being connected between the input rail and the voltage rail;
an MOS output transistor, the output transistor including a channel and a gate, the channel of the output transistor being connected between the output rail and the voltage rail, the gate of the input transistor being connected to the gate of the output transistor;
a switch for connecting the channel of the output transistor to the voltage rail in response to a signal on the control line;
an MOS input cascode transistor, the input cascode transistor including a channel and a gate, the channel of the input cascode transistor connecting the channel of the input transistor to the input rail;
an MOS output cascode transistor, the output cascode transistor including a channel and a gate, the channel of the output cascode transistor connecting the channel of the output transistor to the output rail, the gate of the input cascode transistor being connected to the gate of the output cascode transistor; and
a cascode switch responsive to the signal on the control line to connect the gate of the input cascode transistor to the gate of the output cascode transistor; wherein
closing and opening the switch allows current to flow and not flow respectively between the output rail and the output transistor.

### Claim 25 (depends on 24)

A charge pump circuit according to claim 24, wherein:
the cascode switch includes an MOS cascode control transistor, the cascode control transistor including a channel and a gate, the channel of the cascode control transistor being connected between the gate of the input cascode transistor and the gate of the output cascode transistor, and the gate of the cascode control transistor being connected to the control line.

### Claim 26 (depends on 25)

A charge pump circuit according to claim 25, further comprising:
a cascode resistor connecting the control line to the gate of the cascode control transistor.

### Claim 27

A charge pump for use in a fractional-N frequency synthesizer, the charge pump comprising:
a first charge pump circuit including:
an input rail;
an output rail;
a voltage rail;
a control line;
an MOS input transistor, the input transistor including a channel and a gate, the channel of the input transistor being connected between the input rail and the voltage rail;
an MOS output transistor, the output transistor including a channel and a gate, the channel of the output transistor being connected between the output rail and the voltage rail, the gate of the input transistor being connected to the gate of the output transistor;
a switch for connecting the channel of the output transistor to the voltage rail in response to a signal on the control line;
an MOS input cascode transistor, the input cascode transistor including a channel and a gate, the channel of the input cascode transistor connecting the channel of the input transistor to the input rail;
an MOS output cascode transistor, the output cascode transistor including a channel and a gate, the channel of the output cascode transistor connecting the channel of the output transistor to the output rail, the gate of the input cascode transistor being connected to the gate of the output cascode transistor; and
a cascode switch responsive to the signal on the control line to connect the gate of the input cascode transistor to the gate of the output cascode transistor;
wherein closing and opening said switch allows current to flow and not flow respectively between the output rail and the output transistor and wherein n-MOS transistors are used for pump down; and
a second charge pump circuit including:
an input rail;
an output rail;
a voltage rail;
a control line;
an MOS input transistor, the input transistor including a channel and a gate, the channel of the input transistor being connected between the input rail and the voltage rail;
an MOS output transistor, the output transistor including a channel and a gate, the channel of the output transistor being connected between the output rail and the voltage rail, the gate of the input transistor being connected to the gate of the output transistor;
a switch for connecting the channel of the output transistor to the voltage rail in response to a signal on the control line;
an MOS input cascode transistor, the input cascode transistor including a channel and a gate, the channel of the input cascode transistor connecting the channel of the input transistor to the input rail;
an MOS output cascode transistor, the output cascode transistor including a channel and a gate, the channel of the output cascode transistor connecting the channel of the output transistor to the output rail, the gate of the input cascode transistor being connected to the gate of the output cascode transistor; and
a cascode switch responsive to the signal on the control line to connect the gate of the input cascode transistor to the gate of the output cascode transistor;
wherein closing and opening the switch allows current to flow and not flow respectively between the output rail and the output transistor, and wherein p-MOS transistors are used for pump up to complement the first charge pump circuit using n-MOS transistors.

### Claim 28 (depends on 27)

A fractional-N frequency synthesizer comprising:
a voltage controlled oscillator;
a fractional N divider connected to the output of the voltage controlled oscillator and providing a divided signal;
a phase comparator for comparing the divided signal with a reference signal and providing a comparison output;
a charge pump according to claim 27 for receiving the comparison output as an input and providing pump down and pump up outputs; and
a filter for filtering a sum of the pump down and pump up outputs and providing the filtered sum as an input to the voltage controlled oscillator.

### Claim 29 (depends on 27)

An integrated circuit including a charge pump according to claim 27.

### Claim 30 (depends on 29)

An integrated circuit according to claim 29 which is a quad band transceiver integrated circuit.

### Claim 31 (depends on 28)

An integrated circuit including a fractional N-frequency synthesizer according to claim 28.

### Claim 32 (depends on 31)

An integrated circuit according to claim 31 which is a quad band transceiver integrated circuit.

### Claim 33 (depends on 27)

A mobile telephone including a charge pump according to claim 27.

### Claim 34 (depends on 28)

A mobile telephone including a fractional N-frequency synthesizer according to claim 28.

### Claim 35 (depends on 29)

An integrated circuit according to claim 29 which is a television tuner integrated circuit.

### Claim 36 (depends on 31)

An integrated circuit according to claim 31 which is a television tuner integrated circuit.

### Claim 37 (depends on 27)

A television receiver including a charge pump according to claim 27.

### Claim 38 (depends on 28)

A television receiving including a fractional-N frequency synthesizer according to claim 28.