# US 7,746,132 B2 · PLL circuit

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- Number: US 7,746,132 B2
- Document ID: US7746132B2
- Status: Granted
- Kind: B2
- Application number: 12/066,000
- Filed: 2006-07-27
- Published: 2009-06-18
- Granted: 2010-06-29
- Earliest claimed: 2005-09-08
- Assignees: Panasonic Corporation
- Inventors: Tatsuo Okamoto; Yukio Arima; Tsuyoshi Ebuchi; Kyoko Hirata
- Web page: https://patentgrep.com/patent/US7746132B2

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/101: {using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence)}
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H03L 7/0995: {the oscillator comprising a ring oscillator}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

## Claims

### Claim 1

A PLL circuit comprising a loop filter for smoothing a current which is pushed and pulled in accordance with a phase difference between a reference clock signal and a feedback clock signal, a voltage-current converting circuit for converting an output voltage of the loop filter into a current, and a current-controlled oscillator for generating an output clock signal based on a current signal output from the voltage-current converting circuit, characterized by comprising:
a current source; and
an initialization switch which, when receiving an initialization signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator and the current source;
a reset switch which, when receiving a reset signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the reset switch being provided between an input terminal of the voltage-current converting circuit and a ground node;
a deadlock detecting circuit for detecting that the PLL circuit is in a deadlock state; and
a control section, connected to the deadlock detecting circuit, for outputting the reset signal when the deadlock state detected by the deadlock detecting circuit continues for a predetermined time or more, and outputting the initialization signal during start-up of the PLL circuit and following the outputting of the reset signal.

### Claim 2 (depends on 1)

The PLL circuit of claim 1, characterized by comprising:
a fractional-N frequency divider for generating the feedback clock signal from the output clock signal; and
a ΔΣ controller for supplying a fractional-N frequency division ratio to the fractional-N frequency divider.

### Claim 3 (depends on 2)

The PLL circuit of claim 2, characterized in that
the ΔΣ controller, when receiving the initialization signal, supplies a predetermined integer frequency-division ratio to the fractional-N frequency divider based on the initialization signal.