# US 7,746,131 B2 · Reset signal filter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,131 B2 - Document ID: US7746131B2 - Status: Granted - Kind: B2 - Application number: 12/344,198 - Filed: 2008-12-24 - Published: 2010-02-04 - Granted: 2010-06-29 - Earliest claimed: 2008-08-01 - Assignees: Novatek Microelectronics Corp. - Inventors: Cheng-Hsun Chan; Che-Li Lin - Web page: https://patentgrep.com/patent/US7746131B2 ## CPC - H03K 17/22: Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal. ## Claims ### Claim 1 A reset signal filter, comprising: a first comparator for comparing a power voltage and a first reference voltage so as to generate a first comparison signal; N flip-flops connected in series, a reset port of each flip-flop receiving the first comparison signal, an input port of each flip-flop being coupled to an output port of a preceding flip-flop, an input port of the first of the N flip-flops receiving a first reset signal, the N flip-flops connected in series registering levels of the first reset signal during N clock periods; a first logic gate, having N input ports coupled to output ports of the N flip-flops connected in series respectively, for determining if the levels of the first reset signal are identical during N clock periods and generating a logic signal; and an output flip-flop, being coupled to the first logic gate, for receiving the logic signal and outputting a second reset signal. ### Claim 2 (depends on 1) The rest signal filter of claim 1, wherein the first logic gate is an AND gate. ### Claim 3 (depends on 1) The rest signal filter of claim 1, wherein the first logic gate is an OR gate. ### Claim 4 (depends on 1) The rest signal filter of claim 1, further comprising: a second logic gate, having N input ports coupled to the output ports of the N flip-flops connected in series respectively; and a multiplexer having input ports coupled to the output ports of the first and second logic gate respectively, a control port coupled to the output port of the output flip-flop, and an output port coupled to the input port of the output flip-flop. ### Claim 5 (depends on 4) The rest signal filter of claim 4, wherein the first logic gate is an OR gate, and the second logic gate is an AND gate. ### Claim 6 (depends on 1) The rest signal filter of claim 1, further comprising a power voltage detector coupled to the input port of the first of the N flip-flops, wherein the power voltage detector comprises: a second comparator for comparing the power voltage and a second reference voltage so as to generate a second comparison signal; and a third logic gate, coupled to the second comparator, for receiving the second comparison signal and the first reset signal so as to output the first reset signal when the power voltage is stable. ### Claim 7 (depends on 6) The rest signal filter of claim 6, wherein the third logic gate is an AND gate. ### Claim 8 (depends on 6) The rest signal filter of claim 6, wherein the third logic gate is an OR gate and the second comparison signal is inputted to the OR gate through an inverter. ### Claim 9 (depends on 1) The rest signal filter of claim 1, wherein the first reset signal is generated by a Schmitt trigger buffer. ### Claim 10 A reset signal filter, comprising: a reset signal detector for receiving a first reset signal to generate a second reset signal, the reset signal detector comprising: a comparator for comparing a power voltage and a reference voltage so as to generate a comparison signal; a non-reset state detection circuit coupled to receive the comparison signal for detecting the first reset signal if the first reset signal remains in a non-reset state over N clock periods; and a reset state detection circuit coupled to receive the comparison signal for detecting the first reset signal if the first reset signal remains in a reset state over N clock periods. ### Claim 11 (depends on 10) The reset signal filter of claim 10, wherein the first reset signal is generated by a Schmitt trigger buffer. ### Claim 12 (depends on 10) The reset signal filter of claim 10, further comprising a power voltage detector coupled to the reset signal detector, for receiving an output signal generated by a Schmitt trigger buffer and generating the first reset signal according to the stability of a power voltage. ### Claim 13 A method of generating a stable reset signal, comprising: comparing a power voltage and a reference voltage so as to generate a comparison signal; receiving a first reset signal; utilizing the comparison signal to determining when the first reset signal remains in a non-reset state; and generating a second reset signal when the first reset signal remains in a non-reset state over N clock periods. ### Claim 14 (depends on 13) The method of claim 13, further comprising: generating the second reset signal when the first reset signal remains in reset state over N clock periods. ### Claim 15 (depends on 13) The method of claim 13, further comprising: generating the first reset signal when a power voltage is stable. ### Claim 16 (depends on 13) The method of claim 13, wherein the first reset signal is generated by a Schmitt trigger buffer.