# US 7,746,123 B2 · Switching system with reduced EMI > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,123 B2 - Document ID: US7746123B2 - Status: Granted - Kind: B2 - Application number: 12/206,905 - Filed: 2008-09-09 - Published: 2010-03-11 - Granted: 2010-06-29 - Earliest claimed: 2008-09-09 - Assignees: Texas Instruments Incorporated - Inventors: Richard Knight Hester; Patrick Peter Siniscalchi - Web page: https://patentgrep.com/patent/US7746123B2 ## CPC - H03K 17/164: {using parallel switching arrangements} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H03K 17/163: {Soft switching} - H03K 2217/0045: Full bridges, determining the direction of the current through the load - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time. ## Claims ### Claim 1 An apparatus comprising: a power supply; a first output; a second output; a composite shunt switch coupled between the first and second outputs; and a composite switch coupled between the power supply and the first output, the composite switch including: a plurality of transistors coupled in parallel; a switch closing delay line having a plurality of switch closing outputs, wherein each switch closing output is coupled to a control input of one of the plurality of transistors; and a switch opening delay line having a plurality of switch opening outputs, wherein each switch opening output is coupled to one of the plurality of switch closing outputs, and wherein the switch closing delay line and switch opening delay line are coupled in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the plurality of transistors have a substantially shaped progression of different sizes with a shape selected from a group consisting of exponential, linear, and quadratic. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the apparatus is adapted to at least partially overlap an opening of the composite switch and a closing of the composite shunt switch so that a substantially exponential increase of an impedance in the composite switch is at least partially concurrent with a substantially exponential reduction of an impedance in the composite shunt switch, such that an inductive continuation of a current flowing through the composite switch is substantially transferred to the composite shunt switch. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising: a second composite switch coupled between the power supply and the second output; a third composite switch coupled between the first output and a ground; a fourth composite switch coupled between the second output and the ground, wherein the first, second, third and fourth composite switches comprise an H-bridge amplifier, the H-bridge amplifier being adapted to close the composite shunt switch when the first, second, third and fourth composite switches are open. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the switch closing delay line further comprises a plurality of resistors having a range of different sizes each switchingly coupled to a different one of the control inputs of the plurality of transistors, and wherein the switch closing delay line having an input coupled to a gate drive signal for the composite switch. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the switch opening line further comprises a plurality of resistors having a range of different sizes each switchingly coupled to a different one of the control inputs of the plurality of transistors, and wherein the switch opening delay line having an input coupled to a gate drive signal for the composite switch, and wherein the range of resistor sizes in the switch closing delay line is arranged from smallest to largest resistance beginning from the input, and wherein the range of resistor sizes in the switch opening delay line is arranged from largest to smallest resistance beginning from the input. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the plurality of resistors in the switch closing delay line are each switching coupled to the plurality of parallel transistors by a PMOS transistor, and the plurality of resistors in the switch opening delay line are each switching coupled to the plurality of parallel transistors by an NMOS transistor. ### Claim 8 (depends on 4) The apparatus of claim 4, further comprising a first biasing circuit coupled to the first output and a second biasing circuit coupled to the second output. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the first biasing circuit and second biasing circuit are adapted to bias the first output and the second output to a voltage level substantially midway between the power supply and the ground. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein an impedance of each of the first biasing circuit and the second biasing circuit is reduced during at least a portion of a period when at least some of the first, second, third and fourth composite switches are being opened and none of the first, second, third and fourth composite switches are being left closed and the composite shunt switch is being closed. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the first biasing circuit comprises a resistor divider coupled between the power supply and the ground and having a biasing output coupled to the first output, and the second biasing circuit comprises a resistor divider coupled between the power supply and the ground and having a biasing output coupled to the second output. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the first biasing circuit further comprises a transistor voltage divider switchingly coupled between the power supply and the ground and having a second biasing output coupled to the first output, and the second biasing circuit comprises a transistor voltage divider switchingly coupled between the power supply and the ground and having a second biasing output coupled to the second output. ### Claim 13 (depends on 4) The apparatus of claim 4, wherein the apparatus is adapted to operate the first, second, third and fourth composite switches and the shunt switch to substantially minimize flyback and shoot-through currents through the first, second, third and fourth composite switches. ### Claim 14 An H-bridge amplifier comprising: a first composite switch coupled between a power supply and a first output; a second composite switch coupled between the first output and a ground; a third composite switch coupled between the power supply and a second output; a fourth composite switch coupled between the second output and the ground; a fifth composite switch coupled between the first output and the second output; wherein the composite switches each comprise a plurality of transistors coupled in parallel, a switch closing delay line having a plurality of switch closing outputs each coupled to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each coupled to one of the plurality of switch closing outputs, wherein the plurality of transistors have a substantially exponential progression of different sizes, and wherein the switch closing delay line and switch opening delay line are coupled in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time, and wherein a timing of the H-bridge amplifier is adapted so that when the first, second, third and fourth composite switches are opened, an inductive current between the first output and the second output is substantially carried through the fifth composite switch; a first bias circuit coupled to the first output; and a second bias circuit coupled to the second output, wherein the bias circuits each comprise a resistor divider coupled between the power supply and the ground and a transistor voltage divider coupled between the power supply and the ground, wherein the resistor divider has a higher impedance than the transistor voltage divider, and wherein the H-bridge amplifier is adapted to enable the transistor voltage divider only during a transition when at least some of the first, second, third and fourth composite switches are being opened and none of the first, second, third and fourth composite switches are being left closed and the fifth composite switch is being closed. ### Claim 15 An apparatus comprising an H-bridge having a first output, a second output, and a plurality of composite output switches, wherein each composite output switch is coupled to at least one of the first and second outputs, wherein each composite output switch includes: a first PMOS transistor that receives a drive signal at its gate; a second PMOS transistor that receives the drive signal at its gate; a first resistor that is coupled to the first PMOS transistor at its drain; a second resistor that is coupled to the second PMOS transistor at its drain, wherein the resistance of the second resistor is greater than that of the first resistor; a first NMOS transistor that receives the drive signal at its gate; a second NMOS transistor that receives the drive signal at its gate; a third resistor that is coupled to the first NMOS transistor at its drain and that is coupled to the first resistor; a fourth resistor that is coupled to the second NMOS transistor at its drain and that is coupled to the second resistor, wherein the resistance of the third resistor is greater than that of the fourth resistor; a first output transistor that is coupled to a node between the first and third resistors at its gate; and a second output transistor that is coupled in parallel with the first output transistor and that is coupled to a node between the second and fourth resistors at its gate. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the apparatus further comprises: a first shunt bias circuit that is coupled to the first output; and a second shunt bias circuit that is coupled to the second output. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the first and second output transistors are NMOS transistors. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein each composite switch further comprises: a first inverter that is coupled to the gates of the first and second PMOS transistors; and a second inverter that is coupled to the gates of the first and second NMOS transistors. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the apparatus further comprises a composite shunt switch that is coupled between the first and second outputs.