# US 7,746,111 B1 · Gating logic circuits in a self-timed integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,111 B1 - Document ID: US7746111B1 - Status: Granted - Kind: B1 - Application number: 12/417,033 - Filed: 2009-04-02 - Granted: 2010-06-29 - Earliest claimed: 2009-04-02 - Assignees: Xilinx, Inc. - Inventors: Brian C. Gaide; Steven P. Young - Web page: https://patentgrep.com/patent/US7746111B1 ## CPC - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17736: Structural details of routing resources - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Circuits for implementing gating logic in a self-timed integrated circuit. An integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. Each output circuit has a data input coupled to an output of the logic circuit, a gating input, and a data output coupled to an output of the logic block. The output circuit is coupled to place a value on the data input onto the data output when the gating input has a first value and the output circuit receives tokens indicating valid new data on both the data input and the gating input of the output circuit. The output circuit is coupled to leave the data output unchanged when the gating input has a second value and the output circuit receives a token indicating valid new data on both the data and gating inputs of the output circuit. ## Claims ### Claim 1 An integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit; and an output circuit having a first data input coupled to a first output of the logic circuit, a gating input coupled to an output of another of the logic blocks, and a data output coupled to a first output of the logic block, wherein the output circuit is coupled to place a value from the first data input onto the data output when the gating input has a first value and the output circuit receives tokens indicating valid new data on both the first data input and the gating input of the output circuit; and wherein the output circuit is coupled to leave the data output unchanged when the gating input has a second value and the output circuit receives a token indicating valid new data on both the first data input and the gating input of the output circuit. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein: the output circuit is coupled to consume the token on the first data input when the second value on the gating input causes the first output of the logic block to remain unchanged. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein: the output circuit further has a second data input coupled to a second output of the logic circuit; and the output circuit is coupled to consume a token on the second data input. ### Claim 4 (depends on 3) The integrated circuit of claim 3, wherein each output circuit comprises a first multiplexer having a first input coupled to the first data input, a second input coupled to the second data input, a select input coupled to the gating input, and an output coupled to the first output of the logic block. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein each output circuit further comprises a second multiplexer having a first input coupled to the first data input, a second input coupled to the second data input, a select input coupled to the gating input, and a data output coupled to a second output of the logic block. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the plurality of logic blocks comprises an array of the logic blocks, and the logic blocks are substantially similar one to another. ### Claim 7 (depends on 6) The integrated circuit of claim 6, wherein for each logic block the gating input is coupled to a gating output of an output circuit in an adjacent logic block in the array. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit comprises a programmable integrated circuit. ### Claim 9 A programmable integrated circuit, comprising: a plurality of logic blocks; and an interconnect structure coupled between the logic blocks, wherein each of the logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having a first output; and a programmable output circuit having a first data input coupled to the first output of the logic circuit and further having an output coupled to the interconnect structure, wherein each output circuit is programmably coupled, in one of a plurality of operating modes of the output circuit, to output a result of implementing a gating function of the first data input, and wherein the gating function in each output circuit is controlled by a gating input comprising a dynamic signal. ### Claim 10 (depends on 9) The programmable integrated circuit of claim 9, wherein for each logic block: the output circuit is further programmably coupled, in the one of the operating modes, to provide a token with the result only when the gating signal has a first value and the output circuit receives tokens indicating valid new data on both the first data input and the gating input. ### Claim 11 (depends on 9) The programmable integrated circuit of claim 9, wherein for each logic block: the output circuit further has a second data input coupled to a second output of the logic circuit; and the output circuit is further programmably coupled, in the one of the operating modes, to consume a token on the second data input. ### Claim 12 (depends on 11) The programmable integrated circuit of claim 11, wherein each output circuit comprises a first multiplexer having a first input coupled to the first data input, a second input coupled to the second data input, a select input coupled to the gating input, and an output coupled to the first output of the logic block. ### Claim 13 (depends on 12) The programmable integrated circuit of claim 12, wherein each output circuit further comprises a second multiplexer having a first input coupled to the first data input, a second input coupled to the second data input, a select input coupled to the gating input, and an output coupled to a second output of the logic block. ### Claim 14 (depends on 9) The programmable integrated circuit of claim 9, wherein: the plurality of logic blocks comprises an array of the logic blocks; the logic blocks are substantially similar one to another; and for each logic block the gating input is coupled to a gating output of an adjacent logic block in the array. ### Claim 15 (depends on 9) The programmable integrated circuit of claim 9, wherein the integrated circuit comprises a programmable logic device (PLD). ### Claim 16 (depends on 9) The programmable integrated circuit of claim 9, wherein for each of the logic blocks: the first data input and the output of the output circuit each comprise an N-bit bus, N being an integer greater than one, and the dynamic signal on the gating input comprises a single-bit value. ### Claim 17 A programmable integrated circuit, comprising: an array of substantially similar programmable logic blocks; and an interconnect structure coupled between the programmable logic blocks, wherein each of the programmable logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having a first output; and an output circuit having a first data input coupled to the first output of the logic circuit and further having an output coupled to the interconnect structure, wherein each output circuit is programmably coupled to output a result of implementing a gating function of the first data input, and wherein the gating function in each output circuit is controlled by a gating input comprising a dynamic signal. ### Claim 18 (depends on 17) The programmable integrated circuit of claim 17, wherein the result is accompanied by a token only when the gating signal has a first value and the output circuit receives tokens indicating valid new data on both the first data input and the gating input. ### Claim 19 (depends on 17) The programmable integrated circuit of claim 17, wherein for each logic block: the output circuit further has a second data input coupled to a second output of the logic circuit; and the output circuit is programmably coupled to consume a token on the second data input. ### Claim 20 (depends on 19) The programmable integrated circuit of claim 19, wherein each output circuit comprises a multiplexer having a first input coupled to the first data input, a second input coupled to the second data input, a select input coupled to the gating input, and an output coupled to the output of the logic block.