# US 7,746,109 B1 · Circuits for sharing self-timed logic > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,109 B1 - Document ID: US7746109B1 - Status: Granted - Kind: B1 - Application number: 12/417,054 - Filed: 2009-04-02 - Granted: 2010-06-29 - Earliest claimed: 2009-04-02 - Assignees: Xilinx, Inc. - Inventors: Steven P. Young; Brian C. Gaide - Web page: https://patentgrep.com/patent/US7746109B1 ## CPC - G06F 7/5324: {partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers} - H03K 19/0966: {Self-timed logic} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17736: Structural details of routing resources - G06F 2207/382: Reconfigurable for different fixed word lengths - G06F 2207/3884: Pipelining - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An exemplary circuit for implementing logic sharing in self-timed circuits includes a shared logic circuit, an input circuit, an output circuit, and a pipelined routing path. The shared logic circuit has first and second self-timed inputs and first and second self-timed outputs. The input circuit is coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the first or second inputs being determined by an arbitration circuit within the input circuit, and further to output a self-timed select signal. The output circuit is coupled to receive the first and second self-timed outputs from the shared logic circuit and to provide a selected one of the first or second outputs, the selected output being determined by the self-timed select signal. The pipelined routing path routes the self-timed enable signal from the input circuit to the output circuit. ## Claims ### Claim 1 A circuit, comprising: a shared logic circuit having first and second self-timed inputs and first and second self-timed outputs; an input circuit coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the first or second inputs being determined by an arbitration circuit within the input circuit, and further to output a self-timed select signal; an output circuit coupled to receive the first and second self-timed outputs from the shared logic circuit and to provide a selected one of the first or second outputs, the selected one of the first or second outputs being determined by the self-timed select signal; and a pipelined routing path routing the self-timed enable signal from the input circuit to the output circuit. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the shared logic circuit, the input circuit, and the output circuit are all implemented in programmable logic blocks substantially similar one to another. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the circuit comprises an integrated circuit comprising an array of the substantially similar logic blocks. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the circuit comprises a programmable logic device (PLD). ### Claim 5 (depends on 1) The circuit of claim 1, wherein a number of pipeline stages in the pipelined routing path is different from a number of pipeline stages in the shared logic circuit. ### Claim 6 (depends on 5) The circuit of claim 5, wherein the number of pipeline stages in the pipelined routing path is less than the number of pipeline stages in the shared logic circuit. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the input circuit comprises an arbiter coupled to arbitrate between two first self-timed input signals corresponding to the first and second self-timed inputs to the shared logic circuit. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the input circuit implements a merge function between two second self-timed input signals, the merge function being controlled by an output of the arbiter. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the output circuit implements an “IF” function between the first and second self-timed outputs of the shared logic circuit, the “IF” function being controlled by the self-timed enable signal. ### Claim 10 A circuit, comprising: a shared logic circuit having first and second self-timed inputs and first and second self-timed outputs; an input circuit having a first self-timed output coupled to the first input of the shared logic circuit, a second self-timed output coupled to the second input of the shared logic circuit, and a self-timed select output; an output circuit having a first self-timed input coupled to the first output of the shared logic circuit, a second self-timed input coupled to the second output of the shared logic circuit, a self-timed select input, and first and second self-timed outputs; and a pipelined routing path routing a self-timed select signal from the select output of the input circuit to the select input of the output circuit; wherein the input circuit is coupled to provide a token with one of the first or second outputs based on a value output by an arbitration circuit within the input circuit; and wherein the output circuit is coupled to provide an output token with one of the first or second outputs based on a value of the self-timed select signal routed from the input circuit through the pipelined routing path. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the shared logic circuit, the input circuit, and the output circuit are all implemented in programmable logic blocks substantially similar one to another. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the circuit comprises an integrated circuit comprising an array of the substantially similar logic blocks. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the circuit comprises a programmable logic device (PLD). ### Claim 14 (depends on 10) The circuit of claim 10, wherein a number of pipeline stages in the pipelined routing path is different from a number of pipeline stages in the shared logic circuit. ### Claim 15 (depends on 14) The circuit of claim 14, wherein the number of pipeline stages in the pipelined routing path is less than the number of pipeline stages in the shared logic circuit. ### Claim 16 (depends on 10) The circuit of claim 10, wherein the input circuit comprises an arbiter coupled to arbitrate between two first self-timed input signals corresponding to the first and second self-timed inputs to the shared logic circuit. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the input circuit implements a merge function between two second self-timed input signals, the merge function being controlled by an output of the arbiter. ### Claim 18 (depends on 10) The circuit of claim 10, wherein the output circuit implements an “IF” function between the first and second self-timed outputs of the shared logic circuit, the “IF” function being controlled by the self-timed enable signal. ### Claim 19 An integrated circuit, comprising: an array of substantially similar programmable logic blocks; and a interconnect structure interconnecting the programmable logic blocks, wherein the array comprises: a first group of the logic blocks programmed to implement a shared logic circuit having first and second self-timed inputs and first and second self-timed outputs; a second group of the logic blocks programmed to implement an input circuit coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the first or second inputs being determined by an arbitration circuit within the input circuit, and further to output a self-timed select signal; and a third group of the logic blocks programmed to implement an output circuit coupled to receive the first and second self-timed outputs from the shared logic circuit and to provide a selected one of the first or second outputs, the selected one of the first or second outputs being determined by the self-timed select signal, and wherein the interconnect structure comprises a pipelined routing path routing the self-timed enable signal from the input circuit to the output circuit. ### Claim 20 (depends on 17) The integrated circuit of claim 17, wherein the integrated circuit comprises a programmable logic device (PLD).