# US 7,746,107 B1 · Redundant configuration memory systems and methods

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- Number: US 7,746,107 B1
- Document ID: US7746107B1
- Status: Granted
- Kind: B1
- Application number: 12/564,781
- Filed: 2009-09-22
- Granted: 2010-06-29
- Earliest claimed: 2007-02-28
- Assignees: Lattice Semiconductor Corporation
- Inventors: Satwant Singh; Chan-Chi Jason Cheng
- Web page: https://patentgrep.com/patent/US7746107B1

## CPC

- H03K 19/17752: for hot reconfiguration
- H03K 19/1776: for memories
- H03K 19/17764: for reliability
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

In one embodiment, a programmable logic device includes a plurality of configuration memory cells and at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells (e.g., identified as a defective memory cell). An address shift register within the device is adapted to provide programming signals to the plurality of configuration memory cells via wordlines. A data shift register within the device is adapted to provide configuration data to the plurality of configuration memory cells via bitlines. The data shift register is further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.

## Claims

### Claim 1

A programmable logic device comprising:
a plurality of configuration memory cells;
at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells;
a plurality of bitlines;
a plurality of wordlines;
an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines; and
a data shift register adapted to provide configuration data to the plurality of configuration memory cells via the bitlines and further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.

### Claim 2 (depends on 1)

The programmable logic device of claim 1, wherein the data shift register is adapted to provide the configuration data from the spare configuration memory cell to the identified memory cell in response to a programming signal from the address shift register.

### Claim 3 (depends on 1)

The programmable logic device of claim 1, wherein the data shift register is adapted to store configuration data intended for the identified configuration memory cell in the spare configuration memory cell in response to an indication that the identified configuration memory cell is defective.

### Claim 4 (depends on 1)

The programmable logic device of claim 1 including non-volatile memory adapted to store information regarding a wordline associated with an identified configuration memory cell.

### Claim 5 (depends on 1)

The programmable logic device of claim 1, wherein the plurality of configuration memory cells forms columns of configuration memory cells, and the spare configuration memory cell is included in at least a column of spare configuration memory cells.

### Claim 6 (depends on 5)

The programmable logic device of claim 5, wherein:
each column of configuration memory cells is coupled to the address shift register via a wordline;
each row of configuration memory cells within the columns is coupled to the data shift register via a pair of bitlines; and
the column of spare configuration memory cells is coupled to the data shift register but not to the address shift register.

### Claim 7 (depends on 6)

The programmable logic device of claim 6, wherein the columns of configuration memory cells are formed into sections with multiple columns, with each section including a column of spare configuration memory cells and a bit line repeater.

### Claim 8 (depends on 7)

The programmable logic device of claim 7, wherein each section includes a wordline repeater.

### Claim 9

A programmable logic device comprising:
a plurality of configuration memory cells;
at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells;
a plurality of bitlines;
a plurality of wordlines;
means for providing programming signals to the plurality of configuration memory cells via the wordlines; and
means for providing configuration data to the plurality of configuration memory cells via the bitlines and for providing configuration data from the spare configuration memory cell to the identified configuration memory cell.

### Claim 10

A programmable logic device comprising:
a plurality of columns of configuration memory cells;
at least one column of spare configuration memory cells adapted to store configuration data for a memory cell identified within a column of configuration memory cells;
an address shift register coupled to the columns of configuration memory cells via wordlines and adapted to provide programming signals to the configuration memory cells; and
a data shift register coupled to the columns of configuration memory cells via bitlines and adapted to provide configuration data to the configuration memory cells,
wherein the data shift register is further coupled to the column of spare configuration memory cells and adapted to provide configuration data from the spare configuration memory cells to a column of configuration memory cells that includes the identified configuration memory cell in response to a programming signal from the address shift register.

### Claim 11 (depends on 10)

The programmable logic device of claim 10, wherein the column of spare configuration memory cells is coupled to the data shift register but not to the address shift register.

### Claim 12 (depends on 10)

The programmable logic device of claim 10, wherein the columns of configuration memory cells are formed into sections with multiple columns, with each section including a column of spare configuration memory cells and a bit line repeater.

### Claim 13 (depends on 12)

The programmable logic device of claim 12, wherein each section includes a wordline repeater.

### Claim 14 (depends on 10)

The programmable logic device of claim 10, wherein the data shift register is adapted to store configuration data intended for a configuration memory cell in the spare configuration memory cell in response to identification of the configuration memory cell.