# US 7,746,106 B1 · Circuits for enabling feedback paths in a self-timed integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,746,106 B1 - Document ID: US7746106B1 - Status: Granted - Kind: B1 - Application number: 12/417,040 - Filed: 2009-04-02 - Granted: 2010-06-29 - Earliest claimed: 2009-04-02 - Assignees: Xilinx, Inc. - Inventors: Brian C. Gaide; Steven P. Young - Web page: https://patentgrep.com/patent/US7746106B1 ## CPC - H03K 19/1736: {in which the wiring can be modified} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17736: Structural details of routing resources - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal. ## Claims ### Claim 1 An integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit having an input coupled to an input of the logic block, and further having first and second outputs; and means for placing, during an initial cycle, a self-timed first data signal on the second output of the logic circuit onto a first output of the logic block, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs of the logic circuit onto the first output of the logic block, wherein the means for placing is coupled to provide an output token with the second data signal during the initial cycle only when a first token is received indicating valid new data on the second output of the logic circuit and a second token is received indicating a valid new value on a select signal controlling selection of the selected one; and wherein the means for placing is coupled to provide the output token with the second data signal during the subsequent cycles only when either one of the following is true: the first output of the logic circuit is the selected one, and tokens are received indicating valid new data on the first output of the logic circuit and on the select signal; or the second output of the logic circuit is the selected one, and tokens are received indicating valid new data on the first and second outputs of the logic circuit and on the select signal. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the means for placing comprises: a multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to receive the select signal, and a data output coupled to the first output of the logic block. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the means for placing further comprises: a latch coupled between the data output of the multiplexer and the first output of the logic block, the latch having an enable input; and gating logic coupled to the enable input of the latch, and further coupled to receive ready signals provided with the first and second outputs of the logic circuit. ### Claim 4 (depends on 3) The integrated circuit of claim 3, wherein the ready signals comprise handshake signals in handshake logic operating in 2-phase mode. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the plurality of logic blocks comprises an array of the logic blocks, and the logic blocks are substantially similar one to another. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein each logic block further comprises: means for placing, during an initial cycle, the self-timed first data signal on the second output of the logic circuit onto a second output of the logic block, and for placing, during subsequent cycles, the self-timed second data signal on the selected one of the first or second outputs of the logic circuit onto the second output of the logic block. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein each logic block further comprises a select multiplexer having a first data input coupled to an output of another of the logic blocks, a second data input, and a data output coupled to provide the select signal. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit comprises a programmable integrated circuit. ### Claim 9 A programmable integrated circuit, comprising: a plurality of logic blocks; and an interconnect structure coupled between the logic blocks, wherein each of the logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; a first multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to receive a select signal, and a data output coupled to the interconnect structure; and control logic coupled to the first multiplexer, the control logic being programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to place, during an initial cycle, a self-timed first data signal on the second output of the logic circuit onto the interconnect structure, and further programmably coupled, when operating in the one of the operating modes, to place, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs of the logic circuit onto the interconnect structure. ### Claim 10 (depends on 9) The programmable integrated circuit of claim 9, wherein: the control logic is programmably coupled, when operating in the one of the operating modes, to provide an output token with the second data signal during the initial cycle only when a first token is received indicating valid new data on the second output of the logic circuit and a second token is received indicating a valid new value on the select signal; and the control logic is further programmably coupled, when operating in the one of the operating modes, to provide the output token with the second data signal during the subsequent cycles only when either of the following is true: the first output of the logic circuit is the selected one, and tokens are received indicating valid new data on the first output of the logic circuit and on the select signal; or the second output of the logic circuit is the selected one, and tokens are received indicating valid new data on the first and second outputs of the logic circuit and on the select signal. ### Claim 11 (depends on 9) The programmable integrated circuit of claim 9, wherein: the plurality of logic blocks comprises an array of the logic blocks; and for each logic block, the select input is coupled to a select output of an adjacent logic block in the array. ### Claim 12 (depends on 9) The programmable integrated circuit of claim 9, wherein each logic block further comprises: a select multiplexer having a first data input coupled to an output of another of the logic blocks, a second data input, and a data output coupled to the select input of the multiplexer. ### Claim 13 (depends on 9) The programmable integrated circuit of claim 9, wherein the programmable integrated circuit comprises a programmable logic device (PLD). ### Claim 14 (depends on 9) The programmable integrated circuit of claim 9, wherein each logic block further comprises: a second multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to receive the select signal, and a data output coupled to the interconnect structure, wherein the second multiplexer is coupled to the control logic. ### Claim 15 (depends on 9) The programmable integrated circuit of claim 9, wherein the first and second data inputs and the data output of the first multiplexer each comprise an N-bit bus, N being an integer greater than one, and the select input comprises a single-bit value. ### Claim 16 (depends on 9) The programmable integrated circuit of claim 9, wherein for at least one of the logic blocks, the interconnect structure comprises a feedback connection between the data output of the first multiplexer and one of the inputs of the logic circuit. ### Claim 17 A programmable integrated circuit, comprising: an array of substantially similar programmable logic blocks; and an interconnect structure coupled between the programmable logic blocks, wherein each of the programmable logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; a programmable multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to receive a select signal, and a data output coupled to the interconnect structure; and control logic coupled to the programmable multiplexer, the control logic being programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to place, during an initial cycle, a self-timed first data signal on the second output of the logic circuit onto the interconnect structure, and further programmably coupled, when operating in the one of the operating modes, to place, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs of the logic circuit onto the interconnect structure. ### Claim 18 (depends on 17) The programmable integrated circuit of claim 17, wherein: the control logic is programmably coupled, when operating in the one of the operating modes, to provide an output token with the second data signal during the initial cycle only when a first token is received indicating valid new data on the second output of the logic circuit and a second token is received indicating a valid new value on the select signal; and the control logic is further programmably coupled, when operating in the one of the operating modes, to provide the output token with the second data signal during the subsequent cycles only when either of the following is true: the first output of the logic circuit is the selected one, and tokens are received indicating valid new data on the first output of the logic circuit and on the select signal; or the second output of the logic circuit is the selected one, and tokens are received indicating valid new data on the first and second outputs of the logic circuit and on the select signal. ### Claim 19 (depends on 17) The programmable integrated circuit of claim 17, wherein for at least one of the logic blocks, the interconnect structure is programmed to implement a feedback connection between the data output of the multiplexer and one of the inputs of the logic circuit. ### Claim 20 (depends on 17) The programmable integrated circuit of claim 17, wherein the programmable integrated circuit comprises a programmable logic device (PLD).